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A Methodology based on Transportation Problem Modeling for Designing Parallel Interleaver Architectures, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2011. ,
An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture, IEEE International Symposium on Circuits and Systems (ISCAS), 2011. ,
Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010. ,
Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010. ,
A Design Flow for Critical Embedded Systems, IEEE Symposium on Industrial Embedded Systems (SIES), 2010. ,
Hierarchical and Multiple- Clock Domain High-Level Synthesis for Low-Power Design on FPGA, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2010. ,
Static Address Generation Easing: a design methodology for parallel interleaver architectures, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing, 2010. ,
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VNS for High Level Synthesis, Proceedings of 8th Metaheuristics International Conference, 2009. ,
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A design flow dedicated to multi-mode architectures for DSP applications, 2007 IEEE/ACM International Conference on Computer-Aided Design, 2007. ,
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Application of a design space exploration tool to enhance interleaver generation, European Signal Processing Conference, 2007. ,
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Behavioral Description Model BDM for Design Space Exploration: a Case Study of His Algorithm for MC-CDMA System, European Signal Processing Conference (EUSIPCO), 2007. ,
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A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver, IEEE International Symposium on Circuits and Systems (ISCAS), 2007. ,
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SystemC'mantic : A high level Modeling and Co-design Framework For Reconfigurable Real Time Systems, Forum on Design Languages (FDL), 2005. ,
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A More Efficient and Flexible DSP Design Flow from Matlab-Simulink, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., 2005. ,
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High-level synthesis under I/O Timing and Memory constraints, 2005 IEEE International Symposium on Circuits and Systems, 2005. ,
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A Methodoly for IP integration in DSP Soc: a case study of a MAP algorithm for turbo decoder, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2004. ,
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IP integration methodology for SoC design, International Conference on Microelectronics (ICM), 2004. ,
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A Methodoly for Timing and Structural Communication Refinement in DSP Systems, International Conference on Microelectronics (ICM), 2004. ,
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Communication and Timing Constraints Analysis for IP Design and Integration, IFIP WG 10.5 Very Large Scale Integration of System-on-Chip Conference (VLSI-SOC), 2003. ,
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Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder, 9th International Conference on Electronics, Circuits and Systems, 2002. ,
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IP Cores Integration in DSP System- On-Chip Designs, European Signal Processing Conference (EUSIPCO), 2002. ,
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Platform-based design for digital signal processing systems: a case study of MPEG-2/JPEG2000 encoder, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002. ,
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An introduction to the SystemC synthesis subset standard, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS '10, 2010. ,
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Ordonnancement et Assignation en Synthèse de Haut Niveau, 9ieme congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF) Février, 2008. ,
Impact du type d'architecture sur la consommation d'une application, Journées Faible Tension Faible consommation, pp.21-23, 2007. ,
Approche Automatique pour le Raffinement des Communications " , Journées Francophones sur l'Adéquation Algorithme, Architecture, 2005. ,
Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels, MAnifestation des Jeunes Chercheurs STIC (MajecSTIC), 2005. ,
Intégration Optimisée de Composants Virtuels orientés TDSI par la Synthèse d'Architecture, Colloque sur le Traitement du Signal et de l'Image (GRETSI), 2004. ,
Réutilisation de Composant Virtuel dans les Systèmes de Télécommunication: Une Etude de Cas MPEG-2, Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA), 2002. ,
Analyse Fonctionnelle des Moyens de communication Proposés dans les Systèmes sur Silicium, Journées Francophones sur l'Adéquation Algorithme, 2002. ,
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Raising the Abstraction Level of Hardware Design " , Special issue on High-Level Synthesis, IEEE Design and Test of Computers, vol.26, issue.4, 2009. ,
GAUT: A High-Level Synthesis Tool for DSP applications High-Level Synthesis: From Algorithm to Digital Circuits, 2008. ,
Advanced Metaheuristics for High-Level Synthesis, 2010. ,
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VNS for High Level Synthesis, Proceedings of 8th Metaheuristics International Conference, 2009. ,
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Synthesis of Multimode digital signal processing systems, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2007. ,
High-level synthesis under I/O Timing and Memory constraints, 2005 IEEE International Symposium on Circuits and Systems, 2005. ,
DOI : 10.1109/ISCAS.2005.1464679
URL : https://hal.archives-ouvertes.fr/hal-00077297
A Methodoly for IP integration in DSP Soc: a case study of a MAP algorithm for turbo decoder, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2004. ,
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Issy les moulineaux), LESTER Durée du projet : 2005-2008 Publications scientifiques Revues internationales Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-Level Synthesis, Journal of Signal Processing Systems, vol.56, pp.2-3, 2009. ,
Multiple Word-Length High-Level Synthesis, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008. ,
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An introduction to the SystemC synthesis subset standard, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS '10, 2010. ,
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A design flow for critical embedded systems, International Symposium on Industrial Embedded System (SIES), 2010. ,
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Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010. ,
Behavioral Description Model BDM for Design Space Exploration: a Case Study of His Algorithm for MC-CDMA System, European Signal Processing Conference (EUSIPCO), 2007. ,
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Design Space Exploration of DSP Applications Based on Behavioral Description Models, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 2006. ,
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URL : https://hal.archives-ouvertes.fr/hal-00105126
SystemC'mantic : A high level Modeling and Co-design Framework For Reconfigurable Real Time Systems, Forum on Design Languages (FDL), 2005. ,
URL : https://hal.archives-ouvertes.fr/hal-00077818
A More Efficient and Flexible DSP Design Flow from Matlab-Simulink, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., 2005. ,
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IP integration methodology for SoC design, International Conference on Microelectronics (ICM), 2004. ,
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A Methodoly for Timing and Structural Communication Refinement in DSP Systems, International Conference on Microelectronics (ICM), 2004. ,
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Approche Automatique pour le Raffinement des Communications, Journées Francophones sur l'Adéquation Algorithme, 2005. ,
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A methodology based on Transportation problem modeling for designing parallel interleaver architectures, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2011. ,
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An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture, IEEE International Symposium on Circuits and Systems (ISCAS), 2011. ,
Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010. ,
Static Address Generation Easing: a design methodology for parallel interleaver architectures, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing, 2010. ,
DOI : 10.1109/ICASSP.2010.5495535
URL : https://hal.archives-ouvertes.fr/hal-00455121
A memory mapping approach for parallel interleaver design with multiples read and write accesses, Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010. ,
DOI : 10.1109/ISCAS.2010.5537955
URL : https://hal.archives-ouvertes.fr/hal-00482682
Application of a design space exploration tool to enhance interleaver generation, European Signal Processing Conference, 2007. ,
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A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver, IEEE International Symposium on Circuits and Systems (ISCAS), 2007. ,
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A design methodology for space-time adapter, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, 2007. ,
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Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels, MAnifestation des Jeunes Chercheurs STIC (MajecSTIC), 2005. ,
IP integration methodology for SoC design, International Conference on Microelectronics (ICM), 2004. ,
High-Level Synthesis for Designing Multimode Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.11, pp.1736-1749, 2010. ,
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Synthesis of Multimode digital signal processing systems, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007. ,
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A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver, IEEE International Symposium on Circuits and Systems (ISCAS), 2007. ,
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A design methodology for space-time adapter, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, 2007. ,
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VNS for High Level Synthesis, Proceedings of 8th Metaheuristics International Conference, 2009. ,
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Multiple Word-Length High-Level Synthesis, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008. ,
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GAUT: A High-Level Synthesis Tool for DSP applications High-Level Synthesis: From Algorithm to Digital Circuits, 2008. ,
Constrained algorithmic IP design for system-on-chip, Integration, the VLSI Journal, vol.40, issue.2, 2007. ,
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A formal method for hardware IP design and integration under I/O and timing constraints, ACM Transactions on Embedded Computing Systems, vol.5, issue.1, pp.29-53, 2006. ,
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A More Efficient and Flexible DSP Design Flow from Matlab-Simulink, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., 2005. ,
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Intégration Optimisée de Composants Virtuels orientés TDSI par la Synthèse d'Architecture, Colloque sur le Traitement du Signal et de l'Image (GRETSI), 2004. ,
Communication and Timing Constraints Analysis for IP Design and Integration, IFIP WG 10.5 Very Large Scale Integration of System-on-Chip Conference (VLSI-SOC), 2003. ,
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IP Cores Integration in DSP System- On-Chip Designs, European Signal Processing Conference (EUSIPCO), 2002. ,
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Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010. ,
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