. P. Coussy, DCT/Q and IQ/IDCT blocks for MPEG encoding, 1999.

C. Chavet, P. Coussy, P. Urard, and E. Martin, Brevets Apparatus for data interleaving algorithm, CNRS ? STMicroelectronics U.S. Patent application, 2009.

]. C. Andriamisaina, P. Coussy, E. Casseau, and C. Chavet, High-Level Synthesis for Designing Multimode Architectures, Articles dans des revues internationales avec comité de lecture, pp.1736-1749, 2010.
DOI : 10.1109/TCAD.2010.2062751

URL : https://hal.archives-ouvertes.fr/hal-00551454

G. P. Coussy, A. Gajski, M. Takach, and . Meredith, An Introduction to High- Level Synthesis " , Special issue on High-Level Synthesis, IEEE Design and Test of Computers, vol.26, issue.4, 2009.

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis, Journal of Signal Processing Systems, vol.5, issue.1, pp.2-3, 2009.
DOI : 10.1007/s11265-008-0235-1

URL : https://hal.archives-ouvertes.fr/hal-00369044

G. P. Coussy, D. Le-breton, and . Heller, Multiple Word-Length High-Level Synthesis, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008.
DOI : 10.1145/6462.6502

URL : https://hal.archives-ouvertes.fr/hal-00369041

E. P. Coussy, P. Casseau, A. Bomel, E. Baganne, and . Martin, Constrained algorithmic IP design for system-on-chip, Integration, the VLSI Journal, vol.40, issue.2, 2007.
DOI : 10.1016/j.vlsi.2006.02.003

URL : https://hal.archives-ouvertes.fr/hal-00153087

E. P. Coussy, P. Casseau, A. Bomel, E. Baganne, and . Martin, A formal method for hardware IP design and integration under I/O and timing constraints, ACM Transactions on Embedded Computing Systems, vol.5, issue.1, pp.29-53, 2006.
DOI : 10.1145/1132357.1132359

URL : https://hal.archives-ouvertes.fr/hal-00077860

]. P. Coussy and A. Takach, Raising the Abstraction Level of Hardware Design " , Special issue on High-Level Synthesis, Articles dans des revues internationales sans comité de lecture, 2009.

]. P. Coussy, C. Chavet, P. Bomel, D. Heller, E. Senn et al., GAUT: A High-Level Synthesis Tool for DSP applications High-Level Synthesis: From Algorithm to Digital Circuits, 2008.

M. K. Trabelsi, P. Sevaux, A. Coussy, K. Rossi, and . Sörensen, Advanced Metaheuristics for High-Level Synthesis, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00490313

. A. Communications-internationales-avec-comité-de-lecture, P. Sani, C. Coussy, E. Chavet, and . Martin, A Methodology based on Transportation Problem Modeling for Designing Parallel Interleaver Architectures, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2011.

]. A. San-2011b, P. Sani, C. Coussy, E. Chavet, and . Martin, An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture, IEEE International Symposium on Circuits and Systems (ISCAS), 2011.

]. A. San-2010a, P. Sani, C. Coussy, E. Chavet, and . Martin, Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010.

. Lha-2010a-]-g, P. Lhairech-lebreton, D. Coussy, E. Heller, and . Martin, Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010.

J. Vincent-lefftz, H. Bertrand, C. Cassé, P. Clienti, L. Coussy et al., A Design Flow for Critical Embedded Systems, IEEE Symposium on Industrial Embedded Systems (SIES), 2010.

. Lha-2010b-]-g, P. Lhairech-lebreton, E. Coussy, and . Martin, Hierarchical and Multiple- Clock Domain High-Level Synthesis for Low-Power Design on FPGA, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2010.

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Static Address Generation Easing: a design methodology for parallel interleaver architectures, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing, 2010.
DOI : 10.1109/ICASSP.2010.5495535

URL : https://hal.archives-ouvertes.fr/hal-00455121

P. C. Chavet and . Coussy, A memory mapping approach for parallel interleaver design with multiples read and write accesses, Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010.
DOI : 10.1109/ISCAS.2010.5537955

URL : https://hal.archives-ouvertes.fr/hal-00482682

A. P. Coussy, M. Rossi, K. Sevaux, K. Sörensen, and . Trabelsi, VNS for High Level Synthesis, Proceedings of 8th Metaheuristics International Conference, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00414328

C. C. Chavet, P. Andriamisaina, E. Coussy, E. Casseau, P. Juin et al., A design flow dedicated to multi-mode architectures for DSP applications, 2007 IEEE/ACM International Conference on Computer-Aided Design, 2007.
DOI : 10.1109/ICCAD.2007.4397331

URL : https://hal.archives-ouvertes.fr/hal-00167927

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Application of a design space exploration tool to enhance interleaver generation, European Signal Processing Conference, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00154025

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Behavioral Description Model BDM for Design Space Exploration: a Case Study of His Algorithm for MC-CDMA System, European Signal Processing Conference (EUSIPCO), 2007.
URL : https://hal.archives-ouvertes.fr/hal-00153080

P. C. Chavet, P. Coussy, E. Urard, and . Martin, A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver, IEEE International Symposium on Circuits and Systems (ISCAS), 2007.
URL : https://hal.archives-ouvertes.fr/hal-00153994

P. C. Andriamisaina, E. Coussy, and . Casseau, Synthesis of Multimode digital signal processing systems, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007.
DOI : 10.1109/AHS.2007.100

URL : https://hal.archives-ouvertes.fr/hal-00153086

P. C. Chavet, P. Coussy, E. Urard, and . Martin, A design methodology for space-time adapter, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, 2007.
DOI : 10.1145/1228784.1228868

URL : https://hal.archives-ouvertes.fr/hal-00153789

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Design Space Exploration of DSP Applications Based on Behavioral Description Models, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, p.38, 2006.
DOI : 10.1109/SIPS.2006.352589

URL : https://hal.archives-ouvertes.fr/hal-00105126

S. L. Kriaa, E. Adriano, R. Vaumorin, F. Nouacer, S. Blanc et al., SystemC'mantic : A high level Modeling and Co-design Framework For Reconfigurable Real Time Systems, Forum on Design Languages (FDL), 2005.
URL : https://hal.archives-ouvertes.fr/hal-00077818

G. P. Coussy, P. Corre, E. Bomel, E. Senn, and . Martin, A More Efficient and Flexible DSP Design Flow from Matlab-Simulink, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., 2005.
DOI : 10.1109/ICASSP.2005.1416240

URL : https://hal.archives-ouvertes.fr/hal-00077301

G. P. Coussy, P. Corre, E. Bomel, E. Senn, and . Martin, High-level synthesis under I/O Timing and Memory constraints, 2005 IEEE International Symposium on Circuits and Systems, 2005.
DOI : 10.1109/ISCAS.2005.1464679

URL : https://hal.archives-ouvertes.fr/hal-00077297

D. P. Coussy, A. Gnaëdig, A. Nafkha, E. Baganne, E. Boutillon et al., A Methodoly for IP integration in DSP Soc: a case study of a MAP algorithm for turbo decoder, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2004.
URL : https://hal.archives-ouvertes.fr/hal-00077858

A. , ]. F. Abbes, E. Casseau, M. Abid, P. Coussy et al., IP integration methodology for SoC design, International Conference on Microelectronics (ICM), 2004.
DOI : 10.1109/icm.2004.1434582

URL : https://hal.archives-ouvertes.fr/hal-00077856

J. F. Thabet, P. Legoff, E. Coussy, and . Martin, A Methodoly for Timing and Structural Communication Refinement in DSP Systems, International Conference on Microelectronics (ICM), 2004.
URL : https://hal.archives-ouvertes.fr/hal-00077854

A. P. Coussy, E. Baganne, and . Martin, Communication and Timing Constraints Analysis for IP Design and Integration, IFIP WG 10.5 Very Large Scale Integration of System-on-Chip Conference (VLSI-SOC), 2003.
URL : https://hal.archives-ouvertes.fr/hal-00077861

A. P. Coussy, E. Baganne, and . Martin, Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder, 9th International Conference on Electronics, Circuits and Systems, 2002.
DOI : 10.1109/ICECS.2002.1046273

URL : https://hal.archives-ouvertes.fr/hal-00077869

A. P. Coussy, E. Baganne, and . Martin, IP Cores Integration in DSP System- On-Chip Designs, European Signal Processing Conference (EUSIPCO), 2002.
URL : https://hal.archives-ouvertes.fr/hal-00077873

A. P. Coussy, E. Baganne, and . Martin, Platform-based design for digital signal processing systems: a case study of MPEG-2/JPEG2000 encoder, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002.
DOI : 10.1109/ICCCAS.2002.1179034

URL : https://hal.archives-ouvertes.fr/hal-00077874

A. P. Coussy, E. Baganne, and . Martin, A design methodology for IP integration, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002.
DOI : 10.1109/ISCAS.2002.1010556

URL : https://hal.archives-ouvertes.fr/hal-00077875

A. P. Coussy, E. Baganne, and . Martin, A design methodology for integrating IP into SOC systems, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), 2002.
DOI : 10.1109/CICC.2002.1012825

URL : https://hal.archives-ouvertes.fr/hal-00077876

P. G. Savaton, E. Coussy, E. Casseau, and . Martin, A Methodology for Behavioral Virtual Component Specification Targeting SoC Design with High-Level Synthesis Tools, Proc. of the Forum on Design Languages (FDL), 2001.
URL : https://hal.archives-ouvertes.fr/hal-00077880

O. S. Pillement, D. Sentieys, E. Chillet, P. Casseau, E. Coussy et al., Design and synthesis of behavioral level virtual components, IFIP WG 10.5 Very Large Scale Integration of System-on- Chip Conference (VLSI-SOC), 2001.
URL : https://hal.archives-ouvertes.fr/hal-00077881

]. P. Coussy, A. Takach, M. Mcnamara, and M. Meredith, An introduction to the SystemC synthesis subset standard, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS '10, 2010.
DOI : 10.1145/1878961.1878993

URL : https://hal.archives-ouvertes.fr/hal-00593039

]. P. Coussy, Applying High-Level Synthesis (HLS) in an SoC Flow, Communications internationales invitées sans actes EE Times Virtual Event: System-on-Chip 2011, 2011.

. P. Coussy, An Introduction to High-Level Synthesis " , Embedded tutorial " An Introduction to the SystemC Synthesis Subset Standard, IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS), 2010.

. P. Coussy, High-Level Synthesis of dedicated of dedicated coprocessors, Tutorial on ESL Design and Virtual Prototyping of MPSOCs, IEEE Design Automation Conference DAC, 2009.

. P. Coussy, Multi-Mode Architecture Design with High-Level Synthesis, Europe DATE, 2008.

. P. Coussy, GAUT: A High-Level Synthesis Tool, Highlevel synthesis, ECSI Institute & UBS Workshop, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00489794

. G. Communications-francophones-avec-comité-de-lecture, P. Lhairech-lebreton, E. Coussy, and . Martin, Synthèse d'Architecture Multi-horloges pour la Conception Faible Consommation sur FPGA, Colloque sur le Traitement du Signal et de l'Image (GRETSI), 2011.

P. K. Trabelsi, A. Coussy, M. Rossi, and . Sevaux, Ordonnancement et Assignation en Synthèse de Haut Niveau, 9ieme congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF) Février, 2008.

]. J. Lau-2007a, P. Laurent, and . Coussy, Impact du type d'architecture sur la consommation d'une application, Journées Faible Tension Faible consommation, pp.21-23, 2007.

P. F. Thabet, E. Coussy, and . Martin, Approche Automatique pour le Raffinement des Communications " , Journées Francophones sur l'Adéquation Algorithme, Architecture, 2005.

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels, MAnifestation des Jeunes Chercheurs STIC (MajecSTIC), 2005.

A. P. Coussy, E. Baganne, E. Martin, and . Casseau, Intégration Optimisée de Composants Virtuels orientés TDSI par la Synthèse d'Architecture, Colloque sur le Traitement du Signal et de l'Image (GRETSI), 2004.

A. P. Coussy, E. Baganne, and . Martin, Réutilisation de Composant Virtuel dans les Systèmes de Télécommunication: Une Etude de Cas MPEG-2, Journées Francophones sur l'Adéquation Algorithme Architecture (JFAAA), 2002.

A. P. Coussy, E. Baganne, and . Martin, Analyse Fonctionnelle des Moyens de communication Proposés dans les Systèmes sur Silicium, Journées Francophones sur l'Adéquation Algorithme, 2002.

]. P. Coussy, Communications nationales invitées sans actes Conception d'architectures multi-mode pour les applications de traitement du signal, thème Architecture et logiciel embarqué, 2008.

. P. Coussy, Panorama des techniques de synthèse de haut-niveau, Architecture et logiciel embarqué, 2007.

G. P. Coussy, A. Gajski, M. Takach, and . Meredith, An Introduction to High- Level Synthesis " , Special issue on High-Level Synthesis, IEEE Design and Test of Computers, vol.26, issue.4, 2009.

A. P. Coussy and . Takach, Raising the Abstraction Level of Hardware Design " , Special issue on High-Level Synthesis, IEEE Design and Test of Computers, vol.26, issue.4, 2009.

]. P. Chapitres-de-livre, C. Coussy, P. Chavet, D. Bomel, E. Heller et al., GAUT: A High-Level Synthesis Tool for DSP applications High-Level Synthesis: From Algorithm to Digital Circuits, 2008.

M. K. Trabelsi, P. Sevaux, A. Coussy, K. Rossi, and . Sörensen, Advanced Metaheuristics for High-Level Synthesis, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00490313

C. G. Lhairech-lebreton, P. Coussy, and E. Martin, Hierarchical and Multiple-Clock Domain High-Level Synthesis for Low-Power Design on FPGA, 2010 International Conference on Field Programmable Logic and Applications, 2010.
DOI : 10.1109/FPL.2010.94

A. P. Coussy, M. Rossi, K. Sevaux, K. Sörensen, and . Trabelsi, VNS for High Level Synthesis, Proceedings of 8th Metaheuristics International Conference, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00414328

C. C. Chavet, P. Andriamisaina, E. Coussy, E. Casseau, P. Juin et al., A design flow dedicated to multi-mode architectures for DSP applications, 2007 IEEE/ACM International Conference on Computer-Aided Design, 2007.
DOI : 10.1109/ICCAD.2007.4397331

URL : https://hal.archives-ouvertes.fr/hal-00167927

]. C. Andria07a, P. Andriamisaina, E. Coussy, and . Casseau, Synthesis of Multimode digital signal processing systems, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), 2007.

G. P. Coussy, P. Corre, E. Bomel, E. Senn, and . Martin, High-level synthesis under I/O Timing and Memory constraints, 2005 IEEE International Symposium on Circuits and Systems, 2005.
DOI : 10.1109/ISCAS.2005.1464679

URL : https://hal.archives-ouvertes.fr/hal-00077297

D. P. Coussy, A. Gnaëdig, A. Nafkha, E. Baganne, E. Boutillon et al., A Methodoly for IP integration in DSP Soc: a case study of a MAP algorithm for turbo decoder, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2004.
URL : https://hal.archives-ouvertes.fr/hal-00077858

. G. Conférences-nationales-[-lha-2011a-]-g, P. Lhairech-lebreton, E. Coussy, and . Martin, Synthèse d'Architecture Multi-horloges pour la Conception Faible Consommation sur FPGA, Colloque sur le Traitement du Signal et de l'Image (GRETSI), 2011.

P. K. Trabelsi, A. Coussy, M. Rossi, and . Sevaux, Ordonnancement et Assignation en Synthèse de Haut Niveau, 9ieme congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF) Février, 2008.

]. J. Lau-2007a, P. Laurent, and . Coussy, Impact du type d'architecture sur la consommation d'une application, Journées Faible Tension Faible consommation, pp.21-23, 2007.

]. F. Thabet, P. Coussy, D. Heller, and E. Martin, Issy les moulineaux), LESTER Durée du projet : 2005-2008 Publications scientifiques Revues internationales Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-Level Synthesis, Journal of Signal Processing Systems, vol.56, pp.2-3, 2009.

G. P. Coussy, D. Le-breton, and . Heller, Multiple Word-Length High-Level Synthesis, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008.
DOI : 10.1145/6462.6502

URL : https://hal.archives-ouvertes.fr/hal-00369041

A. P. Coussy, M. Takach, M. Mcnamara, and . Meredith, An introduction to the SystemC synthesis subset standard, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS '10, 2010.
DOI : 10.1145/1878961.1878993

URL : https://hal.archives-ouvertes.fr/hal-00593039

C. V. Lefftz, J. Bertrand, H. Cassé, C. Clienti, P. Coussy et al., A design flow for critical embedded systems, International Symposium on Industrial Embedded System (SIES), 2010.
DOI : 10.1109/SIES.2010.5551393

URL : https://hal.archives-ouvertes.fr/hal-00517392

. Lha-2010a-]-g, P. Lhairech-lebreton, D. Coussy, E. Heller, and . Martin, Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010.

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Behavioral Description Model BDM for Design Space Exploration: a Case Study of His Algorithm for MC-CDMA System, European Signal Processing Conference (EUSIPCO), 2007.
URL : https://hal.archives-ouvertes.fr/hal-00153080

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Design Space Exploration of DSP Applications Based on Behavioral Description Models, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 2006.
DOI : 10.1109/SIPS.2006.352589

URL : https://hal.archives-ouvertes.fr/hal-00105126

S. L. Kriaa, E. Adriano, R. Vaumorin, F. Nouacer, S. Blanc et al., SystemC'mantic : A high level Modeling and Co-design Framework For Reconfigurable Real Time Systems, Forum on Design Languages (FDL), 2005.
URL : https://hal.archives-ouvertes.fr/hal-00077818

G. P. Coussy, P. Corre, E. Bomel, E. Senn, and . Martin, A More Efficient and Flexible DSP Design Flow from Matlab-Simulink, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., 2005.
DOI : 10.1109/ICASSP.2005.1416240

URL : https://hal.archives-ouvertes.fr/hal-00077301

A. , ]. F. Abbes, E. Casseau, M. Abid, P. Coussy et al., IP integration methodology for SoC design, International Conference on Microelectronics (ICM), 2004.
DOI : 10.1109/icm.2004.1434582

URL : https://hal.archives-ouvertes.fr/hal-00077856

J. F. Thabet, P. Legoff, E. Coussy, and . Martin, A Methodoly for Timing and Structural Communication Refinement in DSP Systems, International Conference on Microelectronics (ICM), 2004.
URL : https://hal.archives-ouvertes.fr/hal-00077854

C. F. Thabet, P. Coussy, and E. Martin, Approche Automatique pour le Raffinement des Communications, Journées Francophones sur l'Adéquation Algorithme, 2005.
URL : https://hal.archives-ouvertes.fr/hal-00077822

C. A. Sani, P. Coussy, C. Chavet, and E. Martin, A methodology based on Transportation problem modeling for designing parallel interleaver architectures, 2011 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2011.
DOI : 10.1109/ICASSP.2011.5946806

]. A. San-2011b, P. Sani, C. Coussy, E. Chavet, and . Martin, An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture, IEEE International Symposium on Circuits and Systems (ISCAS), 2011.

]. A. San-2010a, P. Sani, C. Coussy, E. Chavet, and . Martin, Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010.

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Static Address Generation Easing: a design methodology for parallel interleaver architectures, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing, 2010.
DOI : 10.1109/ICASSP.2010.5495535

URL : https://hal.archives-ouvertes.fr/hal-00455121

P. C. Chavet and . Coussy, A memory mapping approach for parallel interleaver design with multiples read and write accesses, Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010.
DOI : 10.1109/ISCAS.2010.5537955

URL : https://hal.archives-ouvertes.fr/hal-00482682

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Application of a design space exploration tool to enhance interleaver generation, European Signal Processing Conference, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00154025

P. C. Chavet, P. Coussy, E. Urard, and . Martin, A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver, IEEE International Symposium on Circuits and Systems (ISCAS), 2007.
URL : https://hal.archives-ouvertes.fr/hal-00153994

P. C. Chavet, P. Coussy, E. Urard, and . Martin, A design methodology for space-time adapter, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, 2007.
DOI : 10.1145/1228784.1228868

URL : https://hal.archives-ouvertes.fr/hal-00153789

C. C. Chavet, P. Coussy, P. Urard, and E. Martin, Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels, MAnifestation des Jeunes Chercheurs STIC (MajecSTIC), 2005.

. F. Références, E. Abbes, M. Casseau, P. Abid, J. Coussy et al., IP integration methodology for SoC design, International Conference on Microelectronics (ICM), 2004.

]. C. Andriamisaina, P. Coussy, E. Casseau, and C. Chavet, High-Level Synthesis for Designing Multimode Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.29, issue.11, pp.1736-1749, 2010.
DOI : 10.1109/TCAD.2010.2062751

URL : https://hal.archives-ouvertes.fr/hal-00551454

P. C. Andriamisaina, E. Coussy, and . Casseau, Synthesis of Multimode digital signal processing systems, Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007.
DOI : 10.1109/AHS.2007.100

URL : https://hal.archives-ouvertes.fr/hal-00153086

M. Aubury and R. Watts, Handel-C Compiler, Release 1 Documentation and User's Manual, 1995.

]. B. Bailey, G. Martin, and A. Piziali, ESL Design and Verification: A Prescription for Electronic System Level Methodology, 2007.

A. C. Berrou, P. Glavieux, and . Thitimajshima, Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1, Proceedings of ICC '93, IEEE International Conference on Communications, pp.1064-1070, 1993.
DOI : 10.1109/ICC.1993.397441

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Static Address Generation Easing: a design methodology for parallel interleaver architectures, 2010 IEEE International Conference on Acoustics, Speech and Signal Processing, 2010.
DOI : 10.1109/ICASSP.2010.5495535

URL : https://hal.archives-ouvertes.fr/hal-00455121

P. C. Chavet and . Coussy, A memory mapping approach for parallel interleaver design with multiples read and write accesses, Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010.
DOI : 10.1109/ISCAS.2010.5537955

URL : https://hal.archives-ouvertes.fr/hal-00482682

C. Chavet, P. Coussy, P. Urard, and E. Martin, Apparatus for data interleaving algorithm, CNRS ? STMicroelectronics U.S. Patent application, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00369159

C. C. Chavet, P. Andriamisaina, E. Coussy, E. Casseau, P. Juin et al., A design flow dedicated to multi-mode architectures for DSP applications, 2007 IEEE/ACM International Conference on Computer-Aided Design, 2007.
DOI : 10.1109/ICCAD.2007.4397331

URL : https://hal.archives-ouvertes.fr/hal-00167927

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Application of a design space exploration tool to enhance interleaver generation, European Signal Processing Conference, 2007.
URL : https://hal.archives-ouvertes.fr/hal-00154025

P. C. Chavet, P. Coussy, E. Urard, and . Martin, A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band Interleaver, IEEE International Symposium on Circuits and Systems (ISCAS), 2007.
URL : https://hal.archives-ouvertes.fr/hal-00153994

P. C. Chavet, P. Coussy, E. Urard, and . Martin, A design methodology for space-time adapter, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI , GLSVLSI '07, 2007.
DOI : 10.1145/1228784.1228868

URL : https://hal.archives-ouvertes.fr/hal-00153789

P. C. Chavet, P. Coussy, E. Urard, and . Martin, Méthodologie de modélisation et d'implémentation d'adaptateurs spatio-temporels, MAnifestation des Jeunes Chercheurs STIC (MajecSTIC), 2005.

]. L. Chiou, S. Bhunia, and K. Roy, Synthesis of application-specific highly efficient multi-mode cores for embedded systems, ACM Transactions on Embedded Computing Systems, vol.4, issue.1, 2005.
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]. J. Cockx, Efficient modeling of preemption in a virtual prototype, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), 2000.
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]. J. Cong and J. Xu, Simultaneous FU and register binding based on network flow method, Proceedings of the conference on Design, automation and test in Europe (DATE '08), 2008.

A. P. Coussy, M. Takach, M. Mcnamara, and . Meredith, An introduction to the SystemC synthesis subset standard, Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, CODES/ISSS '10, 2010.
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URL : https://hal.archives-ouvertes.fr/hal-00593039

G. P. Coussy, A. Gajski, M. Takach, and . Meredith, An Introduction to High- Level Synthesis " , Special issue on High-Level Synthesis, IEEE Design and Test of Computers, vol.26, issue.4, 2009.

A. P. Coussy and . Takach, Raising the Abstraction Level of Hardware Design " , Special issue on High-Level Synthesis, IEEE Design and Test of Computers, vol.26, issue.4, 2009.

A. P. Coussy, M. Rossi, K. Sevaux, K. Sörensen, and . Trabelsi, VNS for High Level Synthesis, Proceedings of 8th Metaheuristics International Conference, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00414328

G. P. Coussy, D. Le-breton, and . Heller, Multiple Word-Length High-Level Synthesis, EURASIP Journal on Embedded Systems, vol.2008, issue.1, 2008.
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URL : https://hal.archives-ouvertes.fr/hal-00369041

C. P. Coussy, P. Chavet, D. Bomel, E. Heller, E. Senn et al., GAUT: A High-Level Synthesis Tool for DSP applications High-Level Synthesis: From Algorithm to Digital Circuits, 2008.

E. P. Coussy, P. Casseau, A. Bomel, E. Baganne, and . Martin, Constrained algorithmic IP design for system-on-chip, Integration, the VLSI Journal, vol.40, issue.2, 2007.
DOI : 10.1016/j.vlsi.2006.02.003

URL : https://hal.archives-ouvertes.fr/hal-00153087

E. P. Coussy, P. Casseau, A. Bomel, E. Baganne, and . Martin, A formal method for hardware IP design and integration under I/O and timing constraints, ACM Transactions on Embedded Computing Systems, vol.5, issue.1, pp.29-53, 2006.
DOI : 10.1145/1132357.1132359

URL : https://hal.archives-ouvertes.fr/hal-00077860

G. P. Coussy, P. Corre, E. Bomel, E. Senn, and . Martin, A More Efficient and Flexible DSP Design Flow from Matlab-Simulink, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., 2005.
DOI : 10.1109/ICASSP.2005.1416240

URL : https://hal.archives-ouvertes.fr/hal-00077301

G. P. Coussy, P. Corre, E. Bomel, E. Senn, and . Martin, High-level synthesis under I/O Timing and Memory constraints, 2005 IEEE International Symposium on Circuits and Systems, 2005.
DOI : 10.1109/ISCAS.2005.1464679

URL : https://hal.archives-ouvertes.fr/hal-00077297

D. P. Coussy, A. Gnaëdig, A. Nafkha, E. Baganne, E. Boutillon et al., A Methodoly for IP integration in DSP Soc: a case study of a MAP algorithm for turbo decoder, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2004.
URL : https://hal.archives-ouvertes.fr/hal-00077858

A. P. Coussy, E. Baganne, E. Martin, and . Casseau, Intégration Optimisée de Composants Virtuels orientés TDSI par la Synthèse d'Architecture, Colloque sur le Traitement du Signal et de l'Image (GRETSI), 2004.

A. P. Coussy, E. Baganne, and . Martin, Communication and Timing Constraints Analysis for IP Design and Integration, IFIP WG 10.5 Very Large Scale Integration of System-on-Chip Conference (VLSI-SOC), 2003.
URL : https://hal.archives-ouvertes.fr/hal-00077861

A. P. Coussy, E. Baganne, and . Martin, Virtual component IP re-use in telecommunication systems design: a case study of MPEG-2/JPEG2000 encoder, 9th International Conference on Electronics, Circuits and Systems, 2002.
DOI : 10.1109/ICECS.2002.1046273

URL : https://hal.archives-ouvertes.fr/hal-00077869

A. P. Coussy, E. Baganne, and . Martin, IP Cores Integration in DSP System- On-Chip Designs, European Signal Processing Conference (EUSIPCO), 2002.
URL : https://hal.archives-ouvertes.fr/hal-00077873

A. P. Coussy, E. Baganne, and . Martin, Platform-based design for digital signal processing systems: a case study of MPEG-2/JPEG2000 encoder, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, 2002.
DOI : 10.1109/ICCCAS.2002.1179034

URL : https://hal.archives-ouvertes.fr/hal-00077874

A. P. Coussy, E. Baganne, and . Martin, A design methodology for IP integration, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002.
DOI : 10.1109/ISCAS.2002.1010556

URL : https://hal.archives-ouvertes.fr/hal-00077875

A. P. Coussy, E. Baganne, and . Martin, A design methodology for integrating IP into SOC systems, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), 2002.
DOI : 10.1109/CICC.2002.1012825

URL : https://hal.archives-ouvertes.fr/hal-00077876

A. P. Coussy, E. Baganne, and . Martin, Analyse Fonctionnelle des Moyens de communication Proposés dans les Systèmes sur Silicium, Journées Francophones sur l'Adéquation Algorithme, 2002.

]. V. Degalahal, V. , and T. Tuan, Methodology for high level estimation of FPGA power consumption, Proceedings of the Asia and South Pacific Design Automation Conference ASP-DAC, 2005.

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]. S. Dutt, New faster Kernighan-Lin-type graph-partitioning algorithms, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993.
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]. X. Guerin, Approche Efficace de Développement de Logiciel Embarqué pour des Systèmes Multiprocesseurs sur Puce, Thèse de doctorat, 2010.

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]. L. Kriaa, S. Adriano, E. Vaumorin, R. Nouacer, F. Blanc et al., Process Integration, Devices, and Structures SystemC'mantic : A high level Modeling and Co-design Framework For Reconfigurable Real Time Systems, ITRS 2010] International Technology Roadmap for Semiconductors Forum on Design Languages (FDL), 2005.

]. J. Lau-2007a, P. Laurent, and . Coussy, Impact du type d'architecture sur la consommation d'une application, Journées Faible Tension Faible consommation, pp.21-23, 2007.

]. L. Lavagno and E. Sentovich, ECL, Proceedings of the 36th ACM/IEEE conference on Design automation conference , DAC '99, 1999.
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URL : https://hal.archives-ouvertes.fr/hal-00517392

. Lha-2011a-]-g, P. Lhairech-lebreton, E. Coussy, and . Martin, Synthèse d'Architecture Multi-horloges pour la Conception Faible Consommation sur FPGA, Colloque sur le Traitement du Signal et de l'Image (GRETSI), 2011.

. Lha-2010a-]-g, P. Lhairech-lebreton, D. Coussy, E. Heller, and . Martin, Bitwidth-Aware High-Level Synthesis for Designing Low-Power DSP Applications, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010.

. Lha-2010b-]-g, P. Lhairech-lebreton, E. Coussy, and . Martin, Hierarchical and Multiple- Clock Domain High-Level Synthesis for Low-Power Design on FPGA, IEEE International Conference on Field Programmable Logic and Applications (FPL), 2010.

]. S. Liao, S. Tjiang, and R. Gupta, An efficient implementation of reactivity for modeling hardware in the Scenic design environment, Proceedings of the Design Automation Conference, pp.70-75, 1997.

]. J. Mackay-david and R. M. Neal, Near Shannon limit performance of low density parity check codes, Electronics letters, 1996.

]. G. Martin and G. Smith, High-Level Synthesis: Past, Present, and Future " , Special issue on High-Level Synthesis, IEEE Design and Test of Computers, vol.26, issue.4, 2009.

H. Moussa, A. Baghdadi, and M. , Algorithmic C datatypes MPARM: Multi-processor cycle-accurate architectural simulator Binary de Bruijn on-chip network for a flexible multiprocessor LDPC decoder, 45th ACM/IEEE Design Automation Conference (DAC), 2008.

]. O. Muller, A. Baghdadi, and M. , ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding, Proceedings of the Design Automation & Test in Europe Conference, 2006.
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]. J. Muttersbach, T. Villiger, and W. Fichtner, Practical design of globally-asynchronous locally-synchronous systems, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586), 2000.
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]. A. Nafkha, C. Roland, and E. Boutillon, A Near-Optimal Multiuser Detector for MC-CDMA systems Using Geometrical Approach, Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005., 2005.
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]. C. Papadimitriou, K. Steiglitz, and N. J. Usa, Combinatorial Optimization: Algorithms and Complexity Cycle precise core based hardware/software system simulation with predictable event propagation, Proc. 23rd Euromicro Conf, 1997.

O. S. Pillement, D. Sentieys, E. Chillet, P. Casseau, E. Coussy et al., Design and synthesis of behavioral level virtual components, IFIP WG 10.5 Very Large Scale Integration of System-on- Chip Conference (VLSI-SOC), 2001.
URL : https://hal.archives-ouvertes.fr/hal-00077881

]. A. San-2011a, P. Sani, C. Coussy, E. Chavet, and . Martin, A Methodology based on Transportation Problem Modeling for Designing Parallel Interleaver Architectures, IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 2011.

]. A. San-2011b, P. Sani, C. Coussy, E. Chavet, and . Martin, An Approach Based on Edge Coloring of Tripartite Graph for Designing Parallel LDPC Interleaver Architecture, IEEE International Symposium on Circuits and Systems (ISCAS), 2011.

]. A. San-2010a, P. Sani, C. Coussy, E. Chavet, and . Martin, Design of Parallel LDPC Interleaver Architecture: A Bipartite Edge Coloring Approach, IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2010.

P. G. Savaton, E. Coussy, E. Casseau, and . Martin, A Methodology for Behavioral Virtual Component Specification Targeting SoC Design with High-Level Synthesis Tools, Proc. of the Forum on Design Languages (FDL), 2001.
URL : https://hal.archives-ouvertes.fr/hal-00077880

S. Benedetto and G. Montorsi, SoCLib an open platform for virtual prototyping of multiprocessors system on chip (MP-SoC) [en ligneMapping interleaving laws to parallel turbo and LDPC decoder architectures, IEEE Transactions on Information Theory, vol.50, 2002.

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis, Journal of Signal Processing Systems, vol.5, issue.1, pp.2-3, 2009.
DOI : 10.1007/s11265-008-0235-1

URL : https://hal.archives-ouvertes.fr/hal-00369044

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Behavioral Description Model BDM for Design Space Exploration: a Case Study of His Algorithm for MC-CDMA System, European Signal Processing Conference (EUSIPCO), 2007.
URL : https://hal.archives-ouvertes.fr/hal-00153080

P. F. Thabet, D. Coussy, E. Heller, and . Martin, Design Space Exploration of DSP Applications Based on Behavioral Description Models, 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 2006.
DOI : 10.1109/SIPS.2006.352589

URL : https://hal.archives-ouvertes.fr/hal-00105126

P. F. Thabet, E. Coussy, and . Martin, Approche Automatique pour le Raffinement des Communications " , Journées Francophones sur l'Adéquation Algorithme, Architecture, 2005.

J. F. Thabet, P. Legoff, E. Coussy, and . Martin, A Methodoly for Timing and Structural Communication Refinement in DSP Systems, International Conference on Microelectronics (ICM), 2004.
URL : https://hal.archives-ouvertes.fr/hal-00077854

M. K. Trabelsi, P. Sevaux, A. Coussy, K. Rossi, and . Sörensen, Advanced Metaheuristics for High-Level Synthesis, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00490313

]. K. Trabelsi, Méthodes d'optimisation pour la conception sous contraintes de systèmes et de circuits électroniques, Thèse de doctorat, 2009.

P. K. Trabelsi, A. Coussy, M. Rossi, and . Sevaux, Ordonnancement et Assignation en Synthèse de Haut Niveau, 9ieme congrès de la Société Française de Recherche Opérationnelle et d'Aide à la Décision (ROADEF) Février, 2008.

]. M. Thul, F. Gilbert, and N. Wehn, Optimized concurrent interleaving architecture for high-throughput turbo-decoding, 9th International Conference on Electronics, Circuits and Systems, pp.1099-1102, 2002.
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]. P. Urard, J. Yi, H. Kwon, and A. Gouraud, User needs High- Level Synthesis: From Algorithm to Digital Circuits, 2007.