Electric field controlled semiconductor device Cramming more components onto integrated circuits [4] Transistor Count and Moore's Law, Wikipedia Roadmap for 22nm and beyond (Invited Paper) GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO2/TiN FinFET devices Drain-structure design for reduced band-to-band and band-todefect tunneling leakage, Three-electrode circuit element utilizing semiconductor materialsHome2010.htm [7] Emerging Research Devices and Materials Chapters, Updated Editions, International Technology Roadmap for Semiconductors, pp.1520-1528, 1948. ,
Design of ion-implanted MOSFET's with very small physical dimensions, IEEE Journal of Solid-State Circuits, vol.9, issue.5, pp.256-268, 1974. ,
DOI : 10.1109/JSSC.1974.1050511
An MPGA Compatible FPGA Architecture, Proceedings of the IEEE Custom Integrated Circuits Conference, pp.3-6, 1992. ,
DOI : 10.1109/CICC.1992.591107
Adaptive hardware becomes a reality using electrically reconfigurable arrays (ERAs), IEE Colloquium on User-Configurable Logic -Technology and Applications, 1991. ,
An architecture for electrically configurable gate arrays, IEEE Journal of Solid-State Circuits, vol.24, issue.2, pp.394-398, 1989. ,
DOI : 10.1109/4.18600
The flexibility of the QuickLogic FPGA architecture, Proceedings of WESCON '94, pp.688-691, 1994. ,
DOI : 10.1109/WESCON.1994.403515
Architecture and CAD for Deep-Submicron FPGAs, 1999. ,
DOI : 10.1007/978-1-4615-5145-4
Flexibility of interconnection structures for field-programmable gate arrays, IEEE Journal of Solid-State Circuits, vol.26, issue.3, pp.277-282, 1991. ,
DOI : 10.1109/4.75006
The effect of logic block granularity on deep-submicron FPGA performance and density, 2001. ,
Interconnect enhancements for a high-speed PLD architecture, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays , FPGA '02, p.3, 2002. ,
DOI : 10.1145/503048.503050
The Stratix II logic and routing architecture, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays , FPGA '05, p.14, 2005. ,
DOI : 10.1145/1046192.1046195
Low-energy embedded FPGA structures, Proceedings of the 1998 international symposium on Low power electronics and design , ISLPED '98, p.155, 1998. ,
DOI : 10.1145/280756.280873
Dynamic power consumption in Virtex???-II FPGA family, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays , FPGA '02, p.157, 2002. ,
DOI : 10.1145/503048.503072
Methodology for high level estimation of FPGA power consumption, Design Automation Conference, p.657, 2005. ,
Measuring the gap between FPGAs and ASICs, ACM/SIGDA 14th International Symposium on. FPGA, p.21, 2006. ,
Reduce random-logic complexity, Electronic Design, vol.26, issue.17, pp.98-105, 1978. ,
Altera FPGAs Design IDE. http://www.altera.com/products/software/sfw-index.jsp [29] Xilinx ISE: Xilinx FPGAs Design IDE ,
A user programmable reconfigurable gate array, Procedings of the Custom Integrated Circuits Conference, pp.233-235, 1986. ,
Non-volatile programmable memory cell for programmable logic array, 2007. ,
Non-volatile look-up table for an FPGA, US Patent, issue.0007293, 2008. ,
A general purpose, nonvolatile reprogrammable switch, 1996. ,
A Novel Flashbased FPGA Technology with Deep Trench Isolation, pp.32-33, 2007. ,
Parallel Processing with the Perfect Shuffle, IEEE Transactions on Computers, vol.20, issue.2, pp.153-161, 1971. ,
DOI : 10.1109/T-C.1971.223205
New nonvolatile FPGA concept using magnetic tunneling junction, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, pp.2-3, 2006. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00102767
Performance Benefits of Monolithically Stacked 3-D FPGA, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.26, issue.2, pp.216-229, 2007. ,
DOI : 10.1109/TCAD.2006.887920
Neural networks and physical systems with emergent collective computational abilities, Proceedings of the National Academy of Sciences of the United States of America, vol.79, pp.2254-2258, 1982. ,
Neural Networks PC Tools ? A practical guide, 1990. ,
Modeling of dendritic computation: The single dendrite, AIP Conference Proceedings, pp.308-322, 2000. ,
DOI : 10.1063/1.1291269
Analog VLSI and Neural Systems, 1989. ,
Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing, IEEE Transactions on Nanotechnology, vol.6, issue.6, pp.696-710, 2007. ,
DOI : 10.1109/TNANO.2007.907841
One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography, Applied Physics A, vol.280, issue.6, pp.1173-1178, 2005. ,
DOI : 10.1126/science.280.5370.1716
Two-Dimensional Molecular Electronics Circuits, ChemPhysChem, vol.413, issue.6, pp.519-525, 2002. ,
DOI : 10.1002/1439-7641(20020617)3:6<519::AID-CPHC519>3.0.CO;2-2
A 160-kilobit molecular electronic memory patterned at 1011 bits per square centimetre, Nature, vol.6, issue.7126, pp.414-417, 2007. ,
DOI : 10.1038/nature05462
NanoFabrics: spatial computing using molecular electronics, 28th Annual International Symposium on Computer Architecture, pp.178-189, 2001. ,
Digital logic using molecular electronics, IEEE International Solid-State Circuits Conference, pp.204-459, 2002. ,
Stochastic assembly of sublithographic nanoscale interfaces, IEEE Transactions On Nanotechnology, vol.2, issue.3, pp.165-174, 2003. ,
DOI : 10.1109/TNANO.2003.816658
Programmable nanowire circuits for nanoprocessors, Nature, vol.16, issue.7333, pp.240-244, 2011. ,
DOI : 10.1038/nature09749
Programmable logic circuits based on ambipolar CNFET, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.339-340, 2008. ,
DOI : 10.1145/1391469.1391556
Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.622-627, 2009. ,
DOI : 10.1109/DATE.2009.5090742
A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology, Science, vol.280, issue.5370, pp.1716-1721, 1998. ,
DOI : 10.1126/science.280.5370.1716
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.88.5116
Fundamentals of error-correcting codes, 2003. ,
DOI : 10.1017/CBO9780511807077
Design Methods for Misaligned and Mis-positioned Carbon-Nanotube-Immune Circuits, IEEE Transactions on Computer-Aided Design, 2008. ,
Scalable Carbon Nanotube Computational and Storage Circuits Immune to Metallic and Mispositioned Carbon Nanotubes, IEEE Transactions on Nanotechnology, vol.10, issue.4, 2010. ,
DOI : 10.1109/TNANO.2010.2076323
Switching and Memory Characteristics of ZnSe ??? Ge Heterojunctions, Journal of Applied Physics, vol.42, issue.12, p.5076, 1971. ,
DOI : 10.1063/1.1659895
Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses, International Electron Devices Meeting, pp.587-590, 2004. ,
Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V, 2007 IEEE International Electron Devices Meeting, pp.767-770, 2007. ,
DOI : 10.1109/IEDM.2007.4419060
Phenomenological considerations of resistively switching TiO2 in nano crossbar arrays, 10 th International Conference on ULIS, pp.135-138, 2009. ,
Low-Power and Nanosecond Switching in Robust Hafnium Oxide Resistive Memory With a Thin Ti Cap, IEEE Electron Device Letters, vol.31, issue.1, pp.44-46, 2010. ,
A Systematic Investigation of TiN/CuxO/Cu RRAM with Long Retention and Excellent Thermal Stability, 2009 IEEE International Memory Workshop, pp.1-2, 2009. ,
DOI : 10.1109/IMW.2009.5090577
Latching on the Wire and Pipelining in Nanoscale Designs, 3rd Workshop on Non-Silicon Computation (NSC-3), 2004. ,
Combining 2-level logic families in grid-based nanoscale fabrics, 2007 IEEE International Symposium on Nanoscale Architectures, 2007. ,
DOI : 10.1109/NANOARCH.2007.4400864
Impact of nanomanufacturing flow on systematic yield losses in nanoscale fabrics, 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011. ,
DOI : 10.1109/NANOARCH.2011.5941502
Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism, International Electron Devices Meeting, pp.1-4, 2008. ,
Phase-change memory technology with self-aligned ??Trench cell architecture for 90nm node and beyond, Solid-State Electronics, vol.52, issue.9, pp.1467-1472, 2008. ,
DOI : 10.1016/j.sse.2008.04.031
Integrating Phase-Change Memory Cell With Ge Nanowire Diode for Crosspoint Memory—Experimental Demonstration and Analysis, IEEE Transactions on Electron Devices, vol.55, issue.9, pp.2307-2313, 2008. ,
DOI : 10.1109/TED.2008.927631
Current status of the phase change memory and its future, IEEE International Electron Devices Meeting 2003, pp.225-228, 2003. ,
DOI : 10.1109/IEDM.2003.1269271
Phase-change random access memory: A scalable technology, IBM Journal of Research and Development, vol.52, issue.4.5, pp.4-5465, 2008. ,
DOI : 10.1147/rd.524.0465
Nanosecond switching in GeTe phase change memory cells, Applied Physics Letters, vol.95, issue.4, 2009. ,
DOI : 10.1063/1.3191670
A 45nm generation Phase Change Memory technology, 2009 IEEE International Electron Devices Meeting (IEDM), pp.113-116, 2009. ,
DOI : 10.1109/IEDM.2009.5424409
Phase-change memories, physica status solidi (a), vol.2, issue.1, pp.2281-2297, 2008. ,
DOI : 10.1002/pssa.200723561
A novel flash-based FPGA technology with deep trench isolation, IEEE Non, pp.32-33, 2007. ,
Common signature of many-body thermal excitation in structural relaxation and crystallization of chalcogenide glasses, Applied Physics Letters, vol.94, issue.9, p.91906, 2009. ,
DOI : 10.1063/1.3094916
Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices, Journal of Applied Physics, vol.102, issue.5, p.54517, 2007. ,
DOI : 10.1063/1.2773688
Analytical model for low-frequency noise in amorphous chalcogenide-based phase-change memory devices, Journal of Applied Physics, vol.106, issue.5, p.54506, 2009. ,
DOI : 10.1063/1.3160332
Doped In-Ge-Te Phase Change Memory Featuring Stable Operation and Good Data Retention, 2007 IEEE International Electron Devices Meeting, pp.307-310, 2007. ,
DOI : 10.1109/IEDM.2007.4418932
Reliability characterization of Phase Change Memory, 2009 10th Annual Non-Volatile Memory Technology Symposium (NVMTS), pp.7-11, 2009. ,
DOI : 10.1109/NVMT.2009.5429783
Comparative Assessment of GST and GeTe Materials for Application to Embedded Phase-Change Memory Devices, 2009 IEEE International Memory Workshop, pp.1-2, 2009. ,
DOI : 10.1109/IMW.2009.5090585
Electrical Behavior of Phase-Change Memory Cells Based on GeTe, IEEE Electron Device Letters, vol.31, issue.5, pp.488-490, 2010. ,
Thin Film, Japanese Journal of Applied Physics, vol.39, issue.Part 1, No. 5A, pp.2775-2779, 2009. ,
DOI : 10.1143/JJAP.39.2775
Nitrogen-doped Ge2Sb2Te5 films for nonvolatile memory, Journal of Electronic Materials, vol.4085, issue.2, pp.176-181, 2005. ,
DOI : 10.1007/s11664-005-0230-2
Electrochemical and thermochemical memories, 2008 IEEE International Electron Devices Meeting, pp.1-4, 2008. ,
DOI : 10.1109/IEDM.2008.4796675
Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., pp.754-757, 2005. ,
DOI : 10.1109/IEDM.2005.1609463
Field-Programmable Gate Arrays with Embedded Memories, 1992. ,
Compact Modeling of a PCRAM cell, MOS AK workshop, 2010. ,
Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials, IEEE Transactions on Electron Devices, vol.51, issue.5, pp.714-719, 2004. ,
DOI : 10.1109/TED.2004.825805
Magnetoresistance and spin-transfer torque in magnetic tunnel junctions, Journal of Magnetism and Magnetic Materials, vol.320, issue.7, pp.1227-1237, 2008. ,
DOI : 10.1016/j.jmmm.2007.12.008
Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories, IET Computers & Digital Techniques, vol.4, issue.3, pp.211-226, 2010. ,
DOI : 10.1049/iet-cdt.2009.0019
Concept and basic technologies for 3-D IC structure, 1986 International Electron Devices Meeting, pp.488-491, 1986. ,
DOI : 10.1109/IEDM.1986.191227
Die Stacking Technology for Terabit Chip-to-Chip Communications, IEEE Custom Integrated Circuits Conference 2006, pp.587-590, 2006. ,
DOI : 10.1109/CICC.2006.320826
3D integration technology for set-top box application, 2009 IEEE International Conference on 3D System Integration, pp.1-7, 2009. ,
DOI : 10.1109/3DIC.2009.5306561
Laser-induced Epitaxial Growth (LEG) Technology for High Density 3-D Stacked Memory with High Productivity, 2007 IEEE Symposium on VLSI Technology, pp.80-81, 2007. ,
DOI : 10.1109/VLSIT.2007.4339735
Overlay as the key to drive wafer scale 3D integration, Microelectronic Engineering, vol.84, issue.5-8, pp.5-81412, 2007. ,
DOI : 10.1016/j.mee.2007.01.231
Advances in 3D CMOS Sequential Integration, IEEE International device Meeting, 2009. ,
GeOI and SOI 3D monolithic cell integrations for high density applications, Symposium on VLSI Technology, pp.166-167, 2009. ,
Highly cost effective and high performance 65nm S3 (stacked single-crystal Si) SRAM technology with 25F2, viii 0.16um2 cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications, Digest of Technical Papers of Symposium on VLSI Technology, p.220, 2005. ,
High Speed and Highly Cost effective 72M bit density S3 SRAM Technology with Doubly Stacked Si Layers, Peripheral only CoSix layers and Tungsten Shunt W/L Scheme for Standalone and Embedded Memory, Digest of Technical Papers of Symposium on VLSI Technology, p.82, 2007. ,
Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate, IEEE Electron Device Letters, vol.27, issue.11, p.911, 2006. ,
DOI : 10.1109/LED.2006.883286
Three-dimensional metal gate-high-?-GOI CMOSFETs on 1-poly-6-metal 0.18-µm Si devices, IEEE Electron Device Letters, vol.26, issue.2, p.118, 2005. ,
Silicon Device Scaling to the Sub-10-nm Regime, Science, vol.306, issue.5704, pp.2057-2060, 2004. ,
DOI : 10.1126/science.1100731
Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects, IEEE International. Electron Devices Meeting, 2009. ,
3D multichannels and stacked nanowires technologies for new design opportunities in nanoelectronics, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, pp.265-268, 2008. ,
DOI : 10.1109/ICICDT.2008.4567292
Direct Ultrasensitive Electrical Detection of DNA and DNA Sequence Variations Using Nanowire Nanosensors, Nano Letters, vol.4, issue.1, pp.51-54, 2004. ,
DOI : 10.1021/nl034853b
High Performance Silicon Nanowire Field Effect Transistors, Nano Letters, vol.3, issue.2, pp.149-152, 2003. ,
DOI : 10.1021/nl025875l
GaN-based nanowires: From nanometric-scale characterization to light emitting diodes, physica status solidi (a), vol.90, issue.6, pp.1425-1427, 2010. ,
DOI : 10.1002/pssa.200983603
Silicon Vertically Integrated Nanowire Field Effect Transistors, Nano Letters, vol.6, issue.5, pp.973-977, 2006. ,
DOI : 10.1021/nl060166j
Realization of a Silicon Nanowire Vertical Surround-Gate Field-Effect Transistor, Small, vol.104, issue.1, pp.85-88, 2006. ,
DOI : 10.1002/smll.200500181
Carbon-doped GeTe Phase-Change Memory featuring remarkable RESET current reduction, 2010 Proceedings of the European Solid State Device Research Conference, pp.313-316 ,
DOI : 10.1109/ESSDERC.2010.5618230
On Carbon doping to improve GeTe-based Phase-Change Memory data retention at high temperature, 2010 IEEE International Memory Workshop, pp.1-4, 2010. ,
DOI : 10.1109/IMW.2010.5488328
Using OxRRAM memories for improving communications of reconfigurable FPGA architectures, 2011 IEEE/ACM International Symposium on Nanoscale Architectures, pp.8-09, 2011. ,
DOI : 10.1109/NANOARCH.2011.5941485
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support, 2007 International Conference on Field Programmable Logic and Applications, pp.652-656, 2007. ,
DOI : 10.1109/FPL.2007.4380738
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.128.3243
A single lithography vertical NEMS switch, 2011 IEEE 24th International Conference on Micro Electro Mechanical Systems, pp.95-98, 2011. ,
DOI : 10.1109/MEMSYS.2011.5734370
Power modeling and characteristics of field programmable gate arrays, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.11, pp.1712-1724, 2005. ,
Architectures reconfigurables à base de CNTFET double grille, 2008. ,
CNTFET Modeling and Reconfigurable Logic-Circuit Design, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.54, issue.11, pp.2365-2379, 2007. ,
DOI : 10.1109/TCSI.2007.907835
URL : https://hal.archives-ouvertes.fr/hal-00187137
Single-shell carbon nanotubes of 1-nm diameter, Nature, vol.363, issue.6430, pp.603-605, 1993. ,
DOI : 10.1038/363603a0
Electric Field Effect in Atomically Thin Carbon Films, Science, vol.306, issue.5696, pp.666-669, 2004. ,
DOI : 10.1126/science.1102896
The electronic properties of graphene, Reviews of Modern Physics, vol.81, issue.1, pp.109-163, 2009. ,
DOI : 10.1103/RevModPhys.81.109
Current saturation in zero-bandgap, top-gated graphene field-effect transistors, Nature Nanotechnology, vol.97, issue.11, pp.654-659, 2008. ,
DOI : 10.1038/nnano.2008.268
Operation of Graphene Transistors at Gigahertz Frequencies, Nano Letters, vol.9, issue.1, pp.422-426, 2009. ,
DOI : 10.1021/nl803316h
RF performance of top-gated, zero-bandgap graphene field-effect transistors, 2008 IEEE International Electron Devices Meeting, 2008. ,
DOI : 10.1109/IEDM.2008.4796738
Catalyst preparation for CMOS-compatible silicon nanowire synthesis, Nature Nanotechnology, vol.19, issue.10, pp.654-657, 2009. ,
DOI : 10.1038/nnano.2009.234
URL : https://hal.archives-ouvertes.fr/hal-00445734
Epitaxial-Graphene RF Field-Effect Transistors on Si-Face 6H-SiC Substrates, IEEE Electron Device Letters, vol.30, issue.6, pp.650-652, 2008. ,
DOI : 10.1109/LED.2009.2020699
Ultrathin Epitaxial Graphite:?? 2D Electron Gas Properties and a Route toward Graphene-based Nanoelectronics, The Journal of Physical Chemistry B, vol.108, issue.52, pp.19912-19916, 2004. ,
DOI : 10.1021/jp040650f
Chemically Derived, Ultrasmooth Graphene Nanoribbon Semiconductors, Science, vol.319, issue.5867, pp.1229-1232, 2008. ,
DOI : 10.1126/science.1150878
study on energy gap of bilayer graphene nanoribbons with armchair edges, Applied Physics Letters, vol.92, issue.22, p.223106, 2008. ,
DOI : 10.1063/1.2938058
Low-energy electronic properties of the AB-stacked few-layer graphites, Journal of Physics: Condensed Matter, vol.18, issue.26, p.5849, 2006. ,
DOI : 10.1088/0953-8984/18/26/005
theory of gate induced gaps in graphene bilayers, Physical Review B, vol.75, issue.15, p.155115, 2007. ,
DOI : 10.1103/PhysRevB.75.155115
Direct observation of a widely tunable bandgap in bilayer graphene, Nature, vol.102, issue.7248, p.820, 2009. ,
DOI : 10.1038/nature08105
High-Field Electrical Transport in Single-Wall Carbon Nanotubes, Physical Review Letters, vol.84, issue.13, pp.2941-2944, 2000. ,
DOI : 10.1103/PhysRevLett.84.2941
High-Mobility Nanotube Transistor Memory, Nano Letters, vol.2, issue.7, pp.755-759, 2002. ,
DOI : 10.1021/nl025577o
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.465.7813
Ballistic transport in semiconducting carbon nanotubes, AIP Conference Proceedings, pp.401-404, 2001. ,
DOI : 10.1063/1.1426897
Exclusive-OR gate with a single carbon nanotube, Applied Physics Letters, vol.88, issue.5, pp.53119-053119, 2006. ,
DOI : 10.1063/1.2171474
High-Performance Carbon Nanotube Field-Effect Transistor With Tunable Polarities, IEEE Transactions On Nanotechnology, vol.4, issue.5, pp.481-489, 2005. ,
DOI : 10.1109/TNANO.2005.851427
Field-Modulated Carrier Transport in Carbon Nanotube Transistors, Physical Review Letters, vol.89, issue.12, pp.126801-126804, 2002. ,
DOI : 10.1103/PhysRevLett.89.126801
Graphitic Electrical Contacts to Metallic Single-Walled Carbon Nanotubes Using Pt Electrodes, Nano Letters, vol.9, issue.10, pp.3586-3591, 2009. ,
DOI : 10.1021/nl9017995
Wafer-Scale Growth and Transfer of Aligned Single-Walled Carbon Nanotubes, IEEE Transactions on Nanotechnology, vol.8, issue.4, pp.498-504, 2009. ,
DOI : 10.1109/TNANO.2009.2016562
A Compact Model for Dual-Gate One-Dimensional FET: Application to Carbon-Nanotube FETs, IEEE Transactions on Electron Devices, vol.58, issue.1, pp.206-215, 2011. ,
DOI : 10.1109/TED.2010.2082548
Tunneling phenomena in carbon nanotube field-effect transistors, physica status solidi (a), vol.51, issue.4, pp.679-694, 2008. ,
DOI : 10.1002/pssa.200723528
Implementation of Tunneling Phenomena in a CNTFET Compact Model, IEEE Transactions on Electron Devices, vol.56, issue.10, pp.2224-2231, 2009. ,
DOI : 10.1109/TED.2009.2028621
Electronic structure of atomically resolved carbon nanotubes, Nature, vol.391, issue.6662, pp.59-62, 1998. ,
DOI : 10.1038/34139
Dynamically reconfigurable CNTFET logic cell matrix programming method, 2008. ,
NORA: a racefree dynamic CMOS technique for pipelined logic structures, IEEE Journal of Solid-State Circuits, vol.18, issue.3, pp.261-266, 1983. ,
DOI : 10.1109/JSSC.1983.1051937
Logic Gates and Computation from Assembled Nanowire Building Blocks, Science, vol.294, issue.5545, pp.1313-1317, 2001. ,
DOI : 10.1126/science.1066192
Nanowire-based sublithographic programmable logic arrays, Proceeding of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays , FPGA '04, 2004. ,
DOI : 10.1145/968280.968299
Single-crystal metallic nanowires and metal/semiconductor nanowire heterostructures, Nature, vol.285, issue.6995, pp.61-65, 2004. ,
DOI : 10.1038/nature01141
Array-based architecture for FET-based, nanoscale electronics, IEEE Transactions On Nanotechnology, vol.2, issue.1, pp.23-32, 2003. ,
DOI : 10.1109/TNANO.2003.808508
NASICs: A nanoscale fabric for nanoscale microprocessors, 2008 2nd IEEE International Nanoelectronics Conference, pp.24-27, 2008. ,
DOI : 10.1109/INEC.2008.4585651
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.153.3664
Vapour-liquid-solid mechanism of single crystal growth, Applied Physics Letters, vol.4, 1964. ,
Diameter-controlled synthesis of single-crystal silicon nanowires, Applied Physics Letters, vol.78, issue.15, pp.2214-2216, 2001. ,
DOI : 10.1063/1.1363692
Controlled Growth and Structures of Molecular-Scale Silicon Nanowires, Nano Letters, vol.4, issue.3, pp.433-436, 2004. ,
DOI : 10.1021/nl035162i
Vertically aligned Si intrananowire p-n diodes by large-area epitaxial growth, Applied Physics Letters, vol.94, issue.17, p.173105, 2009. ,
DOI : 10.1063/1.3126037
Epitaxial core???shell and core???multishell nanowire heterostructures, Nature, vol.285, issue.6911, pp.57-61, 2002. ,
DOI : 10.1063/1.102280
An introduction to ultrathin organic films: from Langmuir-Blodgett to self assembly, 1991. ,
Logic Minimization Algorithms for VLSI Synthesis, 1984. ,
DOI : 10.1007/978-1-4613-2821-6
Wire-Streaming Processors on 2-D Nanowire Fabrics, Nano Science and Technology Institute, 2005. ,
Large-Scale Hierarchical Organization of Nanowire Arrays for Integrated Nanosystems, Nano Letters, vol.3, issue.9, pp.1255-1259, 2003. ,
DOI : 10.1021/nl0345062
A Continuous Compact Model of Short-Channel Effects for Undoped Cylindrical Gate-All-Around MOSFETs, 9th Workshop on Compact Modeling, pp.793-796, 2010. ,
A unified short-channel compact model for cylindrical surrounding-gate MOSFET, Solid-State Electronics, vol.56, issue.1, pp.40-46, 2011. ,
DOI : 10.1016/j.sse.2010.11.008
URL : https://hal.archives-ouvertes.fr/hal-00596357
CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices, Nanotechnology, vol.16, issue.6, 2005. ,
DOI : 10.1088/0957-4484/16/6/045
Nanoscale molecular-switch crossbar circuits, Nanotechnology, vol.14, issue.4, 2003. ,
DOI : 10.1088/0957-4484/14/4/311
Novel Si-based nanowire devices: Will they serve ultimate MOSFETs scaling or ultimate hybrid integration?, 2008 IEEE International Electron Devices Meeting, 2008. ,
DOI : 10.1109/IEDM.2008.4796804
The fabrication of advanced transistors with plasma doping, Surface and Coatings Technology, vol.156, issue.1-3, pp.262-266, 2002. ,
DOI : 10.1016/S0257-8972(02)00105-6
Architecture approaching the Atomic Scale, Proceedings of the 33rd European Solid-State Circuits Conference, 2007. ,
The effect of LUT and cluster size on deep-submicron FPGA performance and density, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.288-298, 2004. ,
Packetization and routing analysis of on-chip multiprocessor networks, Journal of Systems Architecture, vol.50, issue.2-3, pp.81-104, 2004. ,
DOI : 10.1016/j.sysarc.2003.07.005
High Performance Non-blocking Switch Design in 3D Die-Stacking Technology, 2009 IEEE Computer Society Annual Symposium on VLSI, pp.25-30, 2009. ,
DOI : 10.1109/ISVLSI.2009.53
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure, 2006 IEEE/ACM International Conference on Computer Aided Design, pp.675-679, 2006. ,
DOI : 10.1109/ICCAD.2006.320012
URL : https://hal.archives-ouvertes.fr/hal-01338460
Performances comparison between multilevel hierarchical and mesh FPGA interconnects, International Journal of Electronics, vol.4, issue.3, pp.275-289, 2008. ,
DOI : 10.1126/science.220.4598.671
URL : https://hal.archives-ouvertes.fr/hal-01195976
On a Class of Multistage Interconnection Networks, IEEE Transactions on Computers, vol.29, issue.8, pp.694-702, 1980. ,
A Survey and Comparision of Fault-Tolerant Multistage Interconnection Networks, Computer, vol.20, issue.6, pp.14-27, 1987. ,
DOI : 10.1109/MC.1987.1663586
VPR 5.0: FPGA CAD and Architecture Exploration Tools with Single-Driver Routing, Heterogeneity and Process Scaling, ACM Symposium on FPGAs, pp.133-142, 2009. ,
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '11, 2011. ,
DOI : 10.1145/1950413.1950457
Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications, 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010. ,
DOI : 10.1109/NANOARCH.2010.5510923
Adaptive methods for growing electronic circuits on an imperfect synthetic matrix, Biosystems, vol.73, issue.3, pp.173-204, 2004. ,
DOI : 10.1016/j.biosystems.2003.12.003
FPGA Design with Double-Gate Carbon Nanotube Transistors, The Electro-Chemical Society Transactions, vol.34, issue.1, pp.495-501, 2011. ,
DOI : 10.1149/1.3567706
URL : https://hal.archives-ouvertes.fr/hal-01002089
A very-high-speed field-programmable gate array using metal-to-metal antifuse programmable elements, Microelectronics Journal, vol.23, issue.7, 1992. ,
DOI : 10.1016/0026-2692(92)90067-B
SIS: A System for Sequential Circuit Synthesis, 1992. ,
Using cluster-based logic blocks and timingdriven packing to improve FPGA speed and density, ACM/SIGDA 7 th International symposium on Field programmable gate arrays, pp.37-46, 1999. ,
ROUTABILITY-DRIVEN PACKING: METRICS AND ALGORITHMS FOR CLUSTER-BASED FPGAs, Journal of Circuits, Systems and Computers, vol.13, issue.01, pp.77-100, 2004. ,
DOI : 10.1142/S0218126604001222
Efficient circuit clustering for area and power reduction in FPGAs, ACM Transactions on Design Automation of Electronic Systems, vol.7, issue.4, pp.643-663, 2002. ,
DOI : 10.1145/605440.605448
Improving Timing-Driven FPGA Packing with Physical Information, 2007 International Conference on Field Programmable Logic and Applications, pp.117-123, 2007. ,
DOI : 10.1109/FPL.2007.4380635
Design of Interconnection Networks for Programmable Logic, 2004. ,
DOI : 10.1007/978-1-4757-4941-0
Optimal simultaneous mapping and clustering for FPGA delay optimization, Proceedings of the 43rd annual conference on Design automation , DAC '06, pp.472-477, 2006. ,
DOI : 10.1145/1146909.1147035
Scalable Synthesis and Clustering Techniques Using Decision Diagrams, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.27, issue.3, p.423, 2008. ,
DOI : 10.1109/TCAD.2008.915545
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.538.2016
A novel packing algorithm for sparse crossbar FPGA architectures, International Conference on Solid-State and Integrated-Circuit Technology, pp.2345-2348, 2008. ,
Electronic properties of carbon nanotubes containing defects, Journal of Physics and Chemistry of Solids, vol.58, issue.11, pp.1833-1837, 1997. ,
DOI : 10.1016/S0022-3697(97)00095-4
Bipolar, CMOS and BiCMOS circuit technologies examined for testability, [1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems, pp.1015-1020, 1991. ,
DOI : 10.1109/MWSCAS.1991.251963
Matrice interconnectee de cellules logiques reconfigurables avec une topologie d'interconnexion croisee, 2010. ,
Interconnect Topology for Cell Matrices Based on Low-Power Nanoscale Devices " , Faible Tension Faible Consommation, 2011. ,
A metallic-CNT-tolerant carbon nanotube technology using Asymmetrically-Correlated CNTs (ACCNT), Symposium on VLSI Technology, pp.182-183, 2009. ,
DOI : 10.1109/ted.2010.2053207
Integrated wafer-scale growth and transfer of directional Carbon Nanotubes and misaligned-Carbon-Nanotube-immune logic structures, 2008 Symposium on VLSI Technology, pp.205-206, 2008. ,
DOI : 10.1109/VLSIT.2008.4588619
CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated CircuitsSilicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit ApplicationsMatrix Nanodevice-Based Logic Architectures and Associated Functional Mapping MethodMolecular electronics and reconfigurable logic, 16th Asia and South Pacific Design Automation Conference List of Publications Articles published in refereed publications (journals) [1], pp.337-343466, 2010. ,
Ultra-Fine Grain FPGAs: A Granularity StudyUsing OxRRAM Memories for Improving Communications of Reconfigurable FPGA ArchitecturesCan We Go Towards True 3-D Architectures?", WACI sessionEvaluation of a Crossbar Multiplexer in a Lithography-Based Nanowire Technology, Articles published in refereed international conference proceedings USA. [2] USA. [3] 48th Design Automation Conference (DAC) IEEE International Symposium on Circuits and Systems (ISCAS), pp.8-09, 2011. ,
Emerging Memory Technologies for Reconfigurable Routing in FPGA ArchitecturePhase-Change-Memory-Based Storage Elements for Configurable LogicReducing transistor count in clocked standard cells with ambipolar double-gate FETs, FPGA Design with Double-Gate Carbon Nanotube Transistors IEEE International Conference on Electronics, Circuits and Systems (ICECS) International Conference on Field-Programmable Technology (FPT), 8-10 USA. [9] P.-E. Gaillardon, F. Clermidy, I. O'Connor, R. Daviot, "Reconfigurable Reconfigurable nanoscale logic cells : a comarison study IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.495-501, 2009. ,
Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme, 2009 16th IEEE International Conference on Electronics, Circuits and Systems, (ICECS 2009), pp.13-16, 2009. ,
DOI : 10.1109/ICECS.2009.5410800
Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices, 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009. ,
DOI : 10.1109/NANOARCH.2009.5226348
Cellule Memoire " , FR application 11 52127, Reconfigurable Boolean Cells having a Criss-crossed Nanowire Matrix WO2011070164 PCT application, 2009. ,
xxii A.2.1 Brief Literature Overview. xxiii A.3 Material Change: Ambipolar Carbon Nanotubes, xxii A.2 State Variable Change: Phase-Change xxii A.2.2 Technological Assumptions xxvii A.5 Device Change: 1-D Active Element Structures ,
xxix A.5.2.1 Brief Literature Overview ,
xxxi A.6 Overall Comparison, xxxvii B.2.1.2 Limitations xxxviii B.2.2 Architectures Reconfigurables à base de Composants xxxviii B.2.3 Gabarit Architectural xl B.3 Structures Innovantes pour le Routage et la Configuration ,
lx B.5.3.3 Evaluation des Performances dans le Cas Idéal, lix B.5.3 Proposition 3: Structures Entrecroisées aux Dimensions lxiv B.6 Propositions Architecturales en Ruptures et Analyse de Performances ,