T. Ohsawa, K. Fujita, K. Hatsuda, T. Higashi, T. Shino et al., Design of a 128-Mb SOI DRAM Using the Floating Body Cell (FBC), IEEE Journal of Solid-State Circuits, vol.41, issue.1, pp.41135-145, 2006.
DOI : 10.1109/JSSC.0051.859018

S. Khan and S. Hamdioui, Trends and challenges of sram reliability in the nanoscale era, Design and Technology of Integrated Systems in Nanoscale Era (DTIS) 5th International Conference on, pp.1-6, 2010.

L. Shiao, E. Tsao, and . Cheng, Energy-conserving always-on schemes for a mobile node with multiple interfaces in all-IP network, Personal, Indoor and Mobile Radio Communications PIMRC 2007. IEEE 18th International Symposium on, pp.1-5, 2007.

W. Park, C. Sic-choi, J. Il-woo-lee, and . Jang, Energy efficient multi-function home gateway in always-on home environment, IEEE Transactions on Consumer Electronics, vol.56, issue.1, pp.106-111
DOI : 10.1109/TCE.2010.5439132

D. A. El-dib, Z. Abid, and H. A. Shawkey, Investigating an aggressive mode for drowsy cache cells, 2008 Canadian Conference on Electrical and Computer Engineering, pp.901-000904, 2008.
DOI : 10.1109/CCECE.2008.4564666

B. Davydov and V. Gopkalof, Real time energy consumption monitoring as a tool for the freight trains' dispatching, 4th IET International Conference on Railway Condition Monitoring (RCM 2008), pp.1-2, 2008.
DOI : 10.1049/ic:20080330

B. Cheng, S. Roy, G. Roy, F. Adamu-lema, and A. Asenov, Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells, Solid-State Electronics, vol.49, issue.5, 2005.
DOI : 10.1016/j.sse.2004.09.005

F. Boeuf, M. Sellier, A. Farcy, and T. Skotnicki, An Evaluation of the CMOS Technology Roadmap From the Point of View of Variability, Interconnects, and Power Dissipation, IEEE Transactions on Electron Devices, vol.55, issue.6, pp.1433-1440, 2008.
DOI : 10.1109/TED.2008.921274

W. Dong, P. Li, and G. M. Huang, SRAM dynamic stability: Theory, variability and analysis, 2008 IEEE/ACM International Conference on Computer-Aided Design, pp.378-385, 2008.
DOI : 10.1109/ICCAD.2008.4681601

T. Skotnicki, G. Merckel, and C. Denat, MASTAR - A Model For Analog Simulation Of Subthreshold, Saturation And Weak Avalanche Regions In MOSFETs, [Proceedings] 1993 International Workshop on VLSI Process and Device Modeling (1993 VPAD), pp.146-147, 1993.
DOI : 10.1109/VPAD.1993.724762

M. J. Pelgrom, H. Tuinhout, and M. Vertregt, Transistor matching in analog CMOS applications, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), pp.915-918, 1998.
DOI : 10.1109/IEDM.1998.746503

Z. Guo, A. Carlson, K. T. Liang-teck-pang, T. Duong, B. Liu et al., Large-Scale SRAM Variability Characterization in 45 nm CMOS, IEEE Journal of Solid-State Circuits, vol.44, issue.11, pp.443174-3192, 2009.
DOI : 10.1109/JSSC.2009.2032698

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

S. Chellappa, J. Ni, X. Yao, N. Hindman, J. Velamala et al., In-situ characterization and extraction of SRAM variability, Proceedings of the 47th Design Automation Conference on, DAC '10, pp.47-711, 2010.
DOI : 10.1145/1837274.1837454

T. Fischer, E. Amirante, P. Huber, T. Nirschl, A. Olbrich et al., Analysis of read current and write trip voltage variability from a 1-MB SRAM test structure. Semiconductor Manufacturing, IEEE Transactions on, vol.21, issue.4, pp.534-541, 2008.

T. Azam, B. Cheng, and D. R. Cumming, Variability resilient low-power 7T-SRAM design for nano-scaled technologies, 2010 11th International Symposium on Quality Electronic Design (ISQED), pp.9-14, 2010.
DOI : 10.1109/ISQED.2010.5450414

L. Chang, R. K. Montoye, Y. Nakamura, K. A. Batson, R. J. Eickemeyer et al., An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches, Solid-State Circuits, pp.956-963, 2008.
DOI : 10.1109/JSSC.2007.917509

V. Hu, M. Fan, C. Hsieh, P. Su, and C. Chuang, FinFET SRAM cell optimization considering temporal variability due to NBTI/PBTI and surface orientation, 2010 International Conference on Simulation of Semiconductor Processes and Devices, pp.269-272, 2010.
DOI : 10.1109/SISPAD.2010.5604510

K. Endo, S. O-'uchi, Y. Ishikawa, Y. Liu, T. Matsukawa et al., Variability analysis of TiN FinFET SRAM cell performance and its compensation using Vth-controllable independent double-gate FinFET, Proceedings of 2010 International Symposium on VLSI Technology, System and Application, pp.124-125, 2010.
DOI : 10.1109/VTSA.2010.5488919

X. Zhang, J. Li, M. Grubbs, M. Deal, B. Magyari-kope et al., Physical model of the impact of metal grain work function variability on emerging dual metal gate mosfets and its implication for sram reliability, Electron Devices Meeting (IEDM), pp.1-4, 2009.

S. Mukhopadhyay, K. Kim, and C. Chuang, Device Design and Optimization Methodology for Leakage and Variability Reduction in Sub-45-nm FD/SOI SRAM, IEEE Transactions on Electron Devices, vol.55, issue.1, pp.152-162, 2008.
DOI : 10.1109/TED.2007.911073

R. Tsuchiya, N. Sugii, T. Ishigaki, Y. Morita, H. Yoshimoto et al., Low voltage (vdd 0.6 v) sram operation achieved by reduced threshold voltage variability in sotb (silicon on thin box), VLSI Technology, 2009 Symposium on, pp.150-151, 2009.

V. P. Hu, Y. Wu, M. Fan, P. Su, and C. Chuang, Investigation of static noise margin of Ultra-Thin-Body SOI SRAM cells in subthreshold region using analytical solution of poisson's equation, 2009 International Symposium on VLSI Technology, Systems, and Applications, pp.115-116, 2009.
DOI : 10.1109/VTSA.2009.5159317

M. Suzuki, T. Saraya, K. Shimizu, T. Sakurai, and T. Hiramoto, Post-fabrication self-convergence scheme for suppressing variability in sram cells and logic transistors, VLSI Technology, pp.148-149, 2009.

B. Giraud and A. Amara, Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), pp.201-204, 2008.
DOI : 10.1109/DELTA.2008.98

A. Kumar, H. Qin, P. Ishwar, J. Rabaey, and K. Ramchandran, Fundamental Data Retention Limits in SRAM Standby Experimental Results, 9th International Symposium on Quality Electronic Design (isqed 2008), pp.92-97, 2008.
DOI : 10.1109/ISQED.2008.4479705

J. Wang, A. Singhee, R. A. Rutenbar, and B. H. Calhoun, Statistical modeling for the minimum standby supply voltage of a full SRAM array, 33rd European Solid State Circuits Conference, pp.400-403, 2007.

A. Agarwal, S. Mukhopadhyay, C. H. Kim, A. Raychowdhury, and K. Roy, Leakage power analysis and reduction: models, estimation and tools, Computers and Digital Techniques, IEE Proceedings, pp.353-368, 2005.
DOI : 10.1049/ip-cdt:20045084

]. D. Pramanik, V. Moroz, and X. W. Lin, Process Induced Layout Variability for Sub 90nm Technologies, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, pp.1849-1852, 2006.
DOI : 10.1109/ICSICT.2006.306464

A. J. Bhavnagarwala, X. Tang, and J. D. , The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE Journal of Solid-State Circuits, vol.36, issue.4, pp.658-665, 2001.
DOI : 10.1109/4.913744

M. Yamaoka and H. Onodera, A Detailed Vth-Variation Analysis for Sub-100-nm Embedded SRAM Design, 2006 IEEE International SOC Conference, pp.315-318, 2006.
DOI : 10.1109/SOCC.2006.283905

B. Amelifard, F. Fallah, and M. Pedram, Leakage Minimization of SRAM Cells in a Dual-<formula formulatype="inline"><tex Notation="TeX">$V_t$</tex></formula> and Dual-<formula formulatype="inline"><tex Notation="TeX">$T_{\rm ox}$</tex></formula> Technology, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, issue.7, pp.851-860, 2008.
DOI : 10.1109/TVLSI.2008.2000459

P. Athe and S. Dasgupta, A comparative study of 6T, 8T and 9T decanano SRAM cell, 2009 IEEE Symposium on Industrial Electronics & Applications, pp.889-894, 2009.
DOI : 10.1109/ISIEA.2009.5356318

H. Yamauchi, Embedded SRAM circuit design technologies for a 45nm and beyond, ASIC, 2007. ASICON '07. 7th International Conference on, pp.1028-1033, 2007.

M. M. Khellah, A. Keshavarzi, D. Somasekhar, T. Karnik, and V. De, Read and write circuit assist techniques for improving Vccmin of dense 6T SRAM cell, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, pp.185-188, 2008.
DOI : 10.1109/ICICDT.2008.4567275

T. S. Doorn, J. A. Croon, E. J. Ter-maten, and A. D. Bucchianico, A yield centric statistical design method for optimization of the SRAM active column, 2009 Proceedings of ESSCIRC, pp.352-355, 2009.
DOI : 10.1109/ESSCIRC.2009.5325954

K. Kim, H. Mahmoodi, and K. Roy, A low-power SRAM using bit-line charge-recycling, Solid-State Circuits, pp.446-459, 2008.

S. K. Jain, K. Srivastva, and S. Kainth, A Novel Circuit to Optimize Access Time and Decoding Schemes in Memories, 2010 23rd International Conference on VLSI Design, pp.117-121, 2010.
DOI : 10.1109/VLSI.Design.2010.17

H. Fu, K. Yeo, A. Do, and Z. Kong, Design and performance evaluation of a low-power data-line sram sense amplifier, Integrated Circuits, ISIC '09. Proceedings of the 2009 12th International Symposium on, pp.291-294, 2009.

A. Bhavnagarwala, S. Kosonocky, C. Radens, R. Stawiasz, K. Mann et al., Fluctuation limits & amp; scaling opportunities for CMOS SRAM cells, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 2005.
DOI : 10.1109/IEDM.2005.1609437

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

M. Bhargava, M. P. Mccartney, A. Hoefler, and K. Mai, Low-overhead, digital offset compensated, SRAM sense amplifiers, 2009 IEEE Custom Integrated Circuits Conference, pp.705-708, 2009.
DOI : 10.1109/CICC.2009.5280732

I. Carlson, S. Andersson, S. Natarajan, and A. Alvandpour, A high density, low leakage, 5T SRAM for embedded caches, Proceedings of the 30th European Solid-State Circuits Conference, pp.215-218, 2004.
DOI : 10.1109/ESSCIR.2004.1356656

S. Cosemans, W. Dehaene, and F. Catthoor, A low power embedded SRAM for wireless applications, Solid-State Circuits Conference Proceedings of the 32nd European, pp.291-294, 2006.

M. Wieckowski and M. Margala, A novel five-transistor (5T) sram cell for high performance cache, 2005 Joint 30th International Conference on Infrared and Millimeter Waves and 13th International Conference on Terahertz Electronics, pp.101-102, 2005.
DOI : 10.1109/SOCC.2005.1554469

M. Wieckowski, S. Patil, and M. Margala, Portless SRAMa high-performance alternative to the 6t methodology, Solid-State Circuits, pp.2600-2610, 2007.

M. Wieckowski and M. Margala, A portless SRAM Cell using stunted wordline drivers, 2008 IEEE International Symposium on Circuits and Systems, pp.584-587, 2008.
DOI : 10.1109/ISCAS.2008.4541485

E. Seevinck, P. J. Van-beers, and H. Ontrop, Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's. In Solid-State Circuits, IEEE Journal, vol.26, pp.525-536, 1991.

S. Sundaram, P. Elakkumanan, and R. Sridhar, High speed robust current sense amplifier for nanoscale memories: a winner take all approach, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06), 2006.
DOI : 10.1109/VLSID.2006.98

J. F. Richard and Y. Savaria, High voltage charge pump using standard CMOS technology, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004., pp.317-320, 2004.
DOI : 10.1109/NEWCAS.2004.1359095

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

K. Kobayashi, J. Yamaguchi, and H. Onodera, Measurement results of on-chip IR-drop, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285), pp.521-524
DOI : 10.1109/CICC.2002.1012897