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Optimisation du procédé de réalisation pour l'intégration séquentielle 3D des transistors CMOS FDSOI

Abstract : Low temperature (LT) process is gaining interest in the frame of 3D sequentialintegration where limited thermal budget (<650 ºC) is needed for top FET to preserve bottomFET from any degradation and also in the standard planar integration for achieving ultra-thinEOT and work function control with high-k metal gate without gate-last integration scheme.In this work, LT Solid Phase Epitaxial Regrowth (SPER) has been investigated for reducingthe most critical thermal budget which is dopant activation.From previous works, LT activated devices face several challenges: First, higher junctionleakage limits their application to high performance devices. Secondly, strong deactivation ofthe metastable activated dopants was observed with post anneals. Thirdly, the dopant weakdiffusion makes it difficult to connect the channel with S/D.In this work, it is shown that the use of FDSOI enables to overcome junction leakage andBoron deactivation issues thanks to the defect cutting off and sinking effect of buried oxide.As a consequence, dopant deactivation in FDSOI devices is no longer an issue. Finally,implants conditions of LT transistors have been optimized to reach similar performance thanits standard high temperature counterparts.
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Submitted on : Wednesday, January 9, 2013 - 12:57:12 PM
Last modification on : Friday, March 25, 2022 - 9:41:27 AM
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  • HAL Id : tel-00771763, version 1




Cuiqin Xu. Optimisation du procédé de réalisation pour l'intégration séquentielle 3D des transistors CMOS FDSOI. Autre. Université de Grenoble, 2012. Français. ⟨NNT : 2012GRENT024⟩. ⟨tel-00771763⟩



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