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Compilation automatique pour les FPGAs

Jean-Baptiste Note 1 
1 Algorithmique Matérielle
ENS-PSL - École normale supérieure - Paris
Abstract : This dissertation explores the algorithmic opportunities offered by the high-level synthesis of digital synchronous circuits targeting Programmable Active Memories. We present the implementation of an experimental compiler toolchain which automatically compiles a reconfigurable circuit from its high-level specification. The circuit description is written in DSL (Design Source Language) which is rooted in the Jazz functional programming language. DSL can describe any digital synchronous circuit. DSL can then simulate, synthetize and execute the hardware routine on a Programmable Active Memory. The compiler proceeds in stages from the DSL source-code in order synthetize the circuit from its high-level specification. Each compiler stage generates annotations which specify circuit properties down to a synthetizable form. Most annotations are generated automatically. Manual annotations are part of the syntax of DSL, and can be used by an experienced designer to specify circuit details through source guidance. DSL automatically generates the hardware and software interfaces needed for speedy communication between the circuit and its host. The whole system is thus a fully automatic hardware accelerator for software applications described in DSL. It has been tested on a strong set of algorithms, including a lossless codec, digital dithering algorithms, motion estimation and Harris feature point extraction.
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Submitted on : Thursday, April 4, 2013 - 4:29:37 PM
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  • HAL Id : tel-00807973, version 1


Jean-Baptiste Note. Compilation automatique pour les FPGAs. Performance et fiabilité [cs.PF]. Université Pierre et Marie Curie - Paris VI, 2007. Français. ⟨NNT : 2007PA066483⟩. ⟨tel-00807973⟩



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