S. Lin and D. Costello, Error Control Coding, 1982.

G. J. Forney, Performance of concatenated codes Key papers in the development of coding theory, E. Berlekamp, 1974.

C. Berrou, A. Glavieux, and P. Thitimajshima, Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1, Proceedings of ICC '93, IEEE International Conference on Communications, pp.1064-1070, 1993.
DOI : 10.1109/ICC.1993.397441

S. Dolinar and D. Divsalar, Weight distributions for turbo codes using random and nonrandom permutations The Telecommunications and Data Acquisition Report, Tech. Rep, pp.56-65, 1995.

C. Douillard, M. Jezequel, C. Berrou, J. Tousch, N. Pham et al., The Turbo Code Standard for DVB-RCS, Proc. of the International Symposium on Turbo Codes and Related Topics, pp.535-538, 2000.

O. Takeshita and J. Daniel, New deterministic interleaver designs for turbo codes, IEEE Transactions on Information Theory, vol.46, issue.6, 1988.
DOI : 10.1109/18.868474

O. Takeshita, On maximum contention-free interleavers and permutation polynomials over integer rings, IEEE Transactions on Information Theory, vol.52, issue.3, pp.1249-1253, 2006.
DOI : 10.1109/TIT.2005.864450

A. J. Viterbi, Error bounds for convolutional codes and an asymptotically optimum decoding algorithm, IEEE Transactions on Information Theory, vol.13, issue.2, pp.260-269, 1967.
DOI : 10.1109/TIT.1967.1054010

R. Fano, A heuristic discussion of probabilistic decoding, IEEE Transactions on Information Theory, vol.9, issue.2, pp.64-74, 1963.
DOI : 10.1109/TIT.1963.1057827

J. Forney and G. D. , The viterbi algorithm, Proceedings of the IEEE, vol.61, issue.3, pp.268-278, 1973.
DOI : 10.1109/PROC.1973.9030

J. Hagenauer and P. Hoeher, A Viterbi algorithm with soft-decision outputs and its applications, IEEE Global Telecommunications Conference, 1989, and Exhibition. 'Communications Technology for the 1990s and Beyond, pp.1680-1686, 1989.
DOI : 10.1109/GLOCOM.1989.64230

L. Bahl, J. Cocke, F. Jelinek, and J. Raviv, Optimal decoding of linear codes for minimizing symbol error rate (Corresp.), IEEE Transactions on Information Theory, vol.20, issue.2, pp.284-287, 1974.
DOI : 10.1109/TIT.1974.1055186

P. Robertson, E. Villebrun, and P. Hoeher, A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain, Proceedings IEEE International Conference on Communications ICC '95, pp.1009-1013, 1995.
DOI : 10.1109/ICC.1995.524253

C. Douillard and C. Berrou, Turbo Codes With Rate-<tex>$m/(m+ 1)$</tex>Constituent Convolutional Codes, IEEE Transactions on Communications, vol.53, issue.10, pp.1630-1638, 2005.
DOI : 10.1109/TCOMM.2005.857165

O. Muller, A. Baghdadi, and M. Jézéquel, Exploring Parallel Processing Levels for Convolutional Turbo Decoding, booktitle = ICTTA'06, International Conference on Information and Communication Technologies, from Theory to Applications, pp.2353-2358, 2006.

G. Masera, G. Piccinini, M. R. Roch, and M. Zamboni, VLSI architectures for turbo codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.7, issue.3, pp.369-379, 1999.
DOI : 10.1109/92.784098

E. Boutillon, W. J. Gross, and P. G. Gulak, VLSI architectures for the MAP algorithm, IEEE Transactions on Communications, vol.51, issue.2, pp.175-185, 2003.
DOI : 10.1109/TCOMM.2003.809247

URL : https://hal.archives-ouvertes.fr/hal-00105229

Y. Zhang and K. Parhi, High-Throughput Radix-4 logMAP Turbo Decoder Architecture, 2006 Fortieth Asilomar Conference on Signals, Systems and Computers, pp.1711-1715, 2006.
DOI : 10.1109/ACSSC.2006.355053

H. Moussa, Architecture de Réseaux sur Puce Pour Décodeur Canal Multiprocesseurs, 2009.

O. Muller, Architectures multiprocesseurs monopuces génériques pour turbocommunications haut-débit, 2007.

J. Zhang and M. Fossorier, Shuffled Iterative Decoding, IEEE Transactions on Communications, vol.53, issue.2, pp.209-213, 2005.
DOI : 10.1109/TCOMM.2004.841982

J. Vogt and A. Finger, Improving the max-log-MAP turbo decoder, Electronics Letters, vol.36, issue.23, pp.1937-1939, 2000.
DOI : 10.1049/el:20001357

A. R. Jafri, Architectures multi-ASIP pour turbo récepteur flexible, Ph.D. dissertation, Dépt. Electronique (Institut Mines-Télécom), 2011.

P. Ienne and R. Leupers, Customizable Embedded Processors: Design Technologies and Applications, ser, Series in Systems on Silicon. Massachusetts, 2006.

S. Vassiliadis, S. Wong, G. Gaydadjiev, K. Bertels, G. Kuzmanov et al., The MOLEN polymorphic processor, IEEE Transactions on Computers, vol.53, issue.11, pp.1363-1375, 2004.
DOI : 10.1109/TC.2004.104

X. Chen, A. Minwegen, Y. Hassan, D. Kammler, S. Li et al., FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection Using Reconfigurable ASIP, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, pp.69-76, 2012.
DOI : 10.1109/FCCM.2012.22

K. Karuri, A. Chattopadhyay, X. Chen, D. Kammler, L. Hao et al., A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1281-1294, 2008.
DOI : 10.1109/TVLSI.2008.2002685

A. L. Rosa, L. Lavagno, and C. Passerone, Software development for high-performance, reconfigurable, embedded multimedia systems, IEEE Design and Test of Computers, vol.22, issue.1, pp.28-38, 2005.
DOI : 10.1109/MDT.2005.20

D. Noguet, A. Baghdadi, C. Moy, and G. Maseraonline, Report on the state for the art on hardware architectures for flexible radio and intensive signal processing Available: http://www.newcom-project.eu: 8080/Plone/public-deliverables/research/DR.C.1 final.pdf [33 Coware processor designer homepage Available: http://www.synopsys.com/ Systems Tensilica xtensa 7 homepage Arc configurable cores homepage Stretch software-configurable processors homepage Available

A. Hoffmann, O. Schliebusch, A. Nohl, G. Braun, O. Wahlen et al., A methodology for the design of application specific instruction set processors (ASIP) using the machine description language LISA, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281), pp.625-630, 2001.
DOI : 10.1109/ICCAD.2001.968726

O. Muller, A. Baghdadi, and M. Jezequel, ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding, Proceedings of the Design Automation & Test in Europe Conference, pp.1-6, 2006.
DOI : 10.1109/DATE.2006.244126

A. P. Hekstra, C. Brehm, T. Ilnseher, and N. Wehn, An alternative to metric rescaling in Viterbi decoders A scalable multi-ASIP architecture for standard compliant trellis decoding, Proc. of the International SoC Design Conference (ISOCC), nov, pp.1220-1222, 1989.

. Tensilica, Multi standard turbo decoder -hardware performance, software flexibility, 2011.

J. Kim and I. Park, A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE, 2009 IEEE Custom Integrated Circuits Conference, pp.487-490, 2009.
DOI : 10.1109/CICC.2009.5280790

C. Lin, C. Chen, E. Chang, and A. Wu, A 0.16nJ/bit/iteration 3.38mm2 turbo decoder chip for WiMAX/LTE standards, Proc. of the International Symposium on Integrated Circuits (ISIC), dec, pp.168-171, 2011.
URL : https://hal.archives-ouvertes.fr/in2p3-00018209

M. May, T. Ilnseher, N. Wehn, and W. Raab, A 150 Mbit/s 3GPP LTE Turbo Code Decoder, Proc. Design, Automation and Test in Europe Conference & Exhibition, pp.1420-1425, 2010.

Y. Sun and J. R. Cavallaro, Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder, Integration, the VLSI Journal, vol.44, issue.4, pp.305-315, 2011.
DOI : 10.1016/j.vlsi.2010.07.001

C. Cheng-chi and W. Hsie-chia, Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.57, issue.7, pp.566-570, 2010.
DOI : 10.1109/TCSII.2010.2048481

Y. Gao and M. Soleymani, Triple-binary circular recursive systematic convolutional turbo codes, Proc. of the International Symposium on Wireless Personal Multimedia Communications, pp.951-955, 2002.

J. Kim and I. Park, Bit-Level Extrinsic Information Exchange Method for Double-Binary Turbo Codes, IEEE Transactions on Circuits and Systems II: Express Briefs, vol.56, issue.1, pp.81-85, 2009.
DOI : 10.1109/TCSII.2008.2008523

T. Vogt and N. Wehn, A Reconfigurable ASIP for Convolutional and Turbo Decoding in an SDR Environment, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.1309-1320, 2008.
DOI : 10.1109/TVLSI.2008.2002428

F. Naessens, B. Bougard, S. Bressinck, L. Hollevoet, P. Raghavan et al., A unified instruction set programmable architecture for multi-standard advanced forward error correction, 2008 IEEE Workshop on Signal Processing Systems, pp.31-36, 2008.
DOI : 10.1109/SIPS.2008.4671733

C. Lin, C. Chen, T. Tsai, and A. Wu, Low-Power Memory-Reduced Traceback MAP Decoding for Double-Binary Convolutional Turbo Decoder, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.56, issue.5, pp.1005-1016, 2009.

R. Gallager, Low-density parity-check codes, IEEE Transactions on Information Theory, vol.8, issue.1, 1963.
DOI : 10.1109/TIT.1962.1057683

R. Tanner, A recursive approach to low complexity codes Information Theory, IEEE Transactions on, vol.27, issue.5, pp.533-547, 1981.

S. Lin, L. Chen, J. Xu, and I. Djurdjevic, Near shannon limit quasi-cyclic lowdensity parity-check codes, Proc. of the IEEE Global Telecommunications Conference, GLOBECOM '03, pp.2030-2035, 2003.

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X. Hu, Reduced-Complexity Decoding of LDPC Codes, IEEE Transactions on Communications, vol.53, issue.8, pp.1288-1299, 2005.
DOI : 10.1109/TCOMM.2005.852852

J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier, and X. Hu, Reduced-Complexity Decoding of LDPC Codes, IEEE Transactions on Communications, vol.53, issue.8, 2005.
DOI : 10.1109/TCOMM.2005.852852

H. Moussa, A. Baghdadi, and M. Jezequel, Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder, 2008 IEEE International Symposium on Circuits and Systems, pp.97-100, 2008.
DOI : 10.1109/ISCAS.2008.4541363

Y. Sun and J. Cavallaro, A Flexible LDPC/Turbo Decoder Architecture, Journal of Signal Processing Systems, vol.52, issue.4, pp.1-16, 2010.
DOI : 10.1007/s11265-010-0477-6

A. Niktash, H. Parizi, A. Kamalizad, and N. Bagherzadeh, RECFEC: A Reconfigurable FEC Processor for Viterbi, Turbo, Reed-Solomon and LDPC Coding, 2008 IEEE Wireless Communications and Networking Conference, pp.605-610, 2008.
DOI : 10.1109/WCNC.2008.112

M. Alles, T. Vogt, and N. Wehn, FlexiChaP: A reconfigurable ASIP for convolutional, turbo, and LDPC code decoding, 2008 5th International Symposium on Turbo Codes and Related Topics, pp.84-89, 2008.
DOI : 10.1109/TURBOCODING.2008.4658677

G. Gentile, M. Rovini, and L. Fanucci, A multi-standard flexible turbo/LDPC decoder via ASIC design, 2010 6th International Symposium on Turbo Codes & Iterative Information Processing, pp.294-298
DOI : 10.1109/ISTC.2010.5613886

R. Al-khayat, A. Baghdadi, and M. , ASIP Design and Architecture Efficiency for Multi-standard Turbo Decoding

R. Al-khayat, A. Baghdadi, and M. , Architecture efficiency of application-specific processors: A 170Mbit/s 0.644mm<sup>2</sup> multi-standard turbo decoder, 2012 International Symposium on System on Chip (SoC), pp.11-12, 2012.
DOI : 10.1109/ISSoC.2012.6376368

URL : https://hal.archives-ouvertes.fr/hal-00797562

R. Al-khayat, R. Murugappa, A. Baghdadi, and M. , Area and throughput optimized ASIP for multi-standard turbo decoding, 2011 22nd IEEE International Symposium on Rapid System Prototyping, pp.24-27, 2011.
DOI : 10.1109/RSP.2011.5929979

URL : https://hal.archives-ouvertes.fr/hal-00725134

R. Murugappa, R. Al-khayat, A. Baghdadi, and M. , A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding, 2011 Design, Automation & Test in Europe, pp.14-18, 2011.
DOI : 10.1109/DATE.2011.5763047

URL : https://hal.archives-ouvertes.fr/hal-00632764

P. Reddy, F. Clermidy, R. Al-khayat, A. Baghdadi, and M. , Power consumption analysis and energy efficient optimization for turbo decoder implementation, 2010 International Symposium on System on Chip, pp.29-30, 2010.
DOI : 10.1109/ISSOC.2010.5625565

URL : https://hal.archives-ouvertes.fr/hal-00632782

P. Reddy, F. Clermidy, R. Al-khayat, A. Baghdadi, and M. , TurbASIP power consumption analysis and optimization, System In Package (SOC-SIP) 2010 : Colloque national du groupe de recherches System On Chip, pp.9-11, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00632784