Conditional process execution in the, p.51 ,
158 A.8 structure du buffer créé avec ses indexes d'´ ecriture et de lecture, p.159 ,
161 A.12 Bloc FSM ajoutéajouté`ajoutéà l 162 A.13 FSM initiale avec action a3 multi-tokens, A.11 Macro bloc FSM créé pour lesécrituresles´lesécritures, p.163 ,
166 A.18 Architecture développée pour le codage spatial, 167 A.19 Architecture développée pour le codage de fréquence . . . . . . . . . 168 ,
MPEG-4 part 2 SP implementation comparison, p.111 ,
Design of an Embedded Low Complexity Image Coder using CAL language, DASIP 2009 proceedings, 2009. ,
Fast hardware implementation of an Hadamard transform using RVC-CAL dataflow programming ,
Automatic method for efficient hardware implementation from RVC-CAL dataflow: A LAR coder baseline case study, Journal Of Convergence, vol.1, issue.12, pp.8592-2010 ,
Automatic generation of synthesizable hardware implementation from high level RVC-CAL design, ICASSP 2012: Proceedings of the 37th International Conference on Acoustics Speech and Signal Processing, p.15971600, 2012. ,
Automatic generation of optimized and synthesizable hardware implementation from high level dataflow programs " . VLSI Design, pp.14-2012, 2012. ,
A dataflow description of acc-jpeg coder, the proceedings of 2012 International Conference on Signal Processing and Multimedia Application, 2012. ,
Discrete cosine transfom, IEEE Transactions on Computers, vol.23, pp.90-93, 1974. ,
DOI : 10.1109/t-c.1974.223784
Compilers: principles, techniques, and tools, 1986. ,
ESL design and verification: a prescription for electronic system-level methodology. The Morgan Kaufmann series in systems on silicon, 2007. ,
A unified hardware/software co-synthesis solution for signal processing systems, Proceedings of the 2011 Conference on Design & Architectures for Signal & Image Processing (DASIP), pp.1-6 ,
DOI : 10.1109/DASIP.2011.6136877
URL : https://hal.archives-ouvertes.fr/hal-00717244
Quasi-static scheduling of reconfigurable dataflow graphs for DSP systems, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668), p.84, 2000. ,
DOI : 10.1109/IWRSP.2000.855200
Parameterized dataflow modeling for DSP systems, IEEE Transactions on Signal Processing, vol.49, issue.10, pp.2408-2421, 2001. ,
DOI : 10.1109/78.950795
OpenDF -A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems, First Swedish Workshop on Multi-Core Computing, 2008. ,
URL : https://hal.archives-ouvertes.fr/hal-00398827
Cycle-static dataflow, IEEE Transactions on Signal Processing, vol.44, issue.2, pp.397-408, 1996. ,
DOI : 10.1109/78.485935
A spiral model of software development and enhancement. SIG- SOFT Softw, Eng. Notes, vol.11, pp.14-24, 1986. ,
Quasistatic scheduling of CAL actor networks for reconfigurable video coding, Journal of Signal Processing Systems, pp.1-12, 2008. ,
Ptolemy: A Framework for Simulating and Prototyping Heterogeneous Systems, International Journal of Computer Simulation, vol.4, pp.155-182, 1994. ,
DOI : 10.1016/B978-155860702-6/50048-X
Scheduling dynamic dataflow graphs with bounded memory using the token flow model, IEEE International Conference on Acoustics Speech and Signal Processing, pp.429-432, 1993. ,
DOI : 10.1109/ICASSP.1993.319147
A flexible twolayer external memory management for h.264/avc decoder, SOC Conference, pp.219-222, 2007. ,
Global code motion/global value numbering, ACM SIGPLAN Notices, vol.30, issue.6, pp.246-257, 1995. ,
DOI : 10.1145/223428.207154
Quasi-static scheduling of independent tasks for reactive systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.10, pp.1492-1514, 2005. ,
DOI : 10.1109/TCAD.2005.852038
An Introduction to High-Level Synthesis, IEEE Design & Test of Computers, vol.26, issue.4, pp.8-17, 2009. ,
DOI : 10.1109/MDT.2009.69
URL : https://hal.archives-ouvertes.fr/hal-00447325
GAUT: A High-Level Synthesis Tool for DSP Applications, High-Level Synthesis: From Algorithm to Digital Circuits, pp.147-170, 2008. ,
DOI : 10.1007/978-1-4020-8588-8_9
URL : https://hal.archives-ouvertes.fr/hal-00489794
Efficiently computing static single assignment form and the control dependence graph, ACM Transactions on Programming Languages and Systems, vol.13, issue.4, p.490, 1991. ,
DOI : 10.1145/115372.115320
Adding control-flow to a visual dataflow representation, Program Comprehension, 2005. IWPC 2005. Proceedings. 13th International Workshop on, pp.297-306, 2005. ,
LAR method : From algorithm to synthesis for an embedded low complexity image coder, 2008 3rd International Design and Test Workshop, 2008. ,
DOI : 10.1109/IDT.2008.4802494
LAR method : From algorithm to synthesis for an embedded low complexity image coder, 2008 3rd International Design and Test Workshop, 2008. ,
DOI : 10.1109/IDT.2008.4802494
Color LAR Codec: A Color Image Representation and Compression Scheme Based on Local Resolution Adjustment and Self-Extracting Region Representation, IEEE Transactions on Circuits and Systems for Video Technology, vol.17, issue.8 ,
DOI : 10.1109/TCSVT.2007.897112
oAW xText: A framework for textual DSLs, Workshop on Modeling Symposium at Eclipse Summit, 2006. ,
An introduction to the Caltrop actor language, 2001. ,
Hardware-software cosynthesis for microcontrollers, IEEE Design & Test of Computers, vol.10, issue.4, pp.64-75, 1993. ,
DOI : 10.1109/54.245964
Run length codings, IEEE Transactions on Information Theory, issue.7, pp.12-399, 1966. ,
An LLVM-based decoder for MPEG Reconfigurable Video Coding, 2010 IEEE Workshop On Signal Processing Systems, pp.81-86, 2010. ,
DOI : 10.1109/SIPS.2010.5624767
URL : https://hal.archives-ouvertes.fr/hal-00560029
LLVM-based and scalable MPEG-RVC decoder, Journal of Real-Time Image Processing, vol.83, issue.5, pp.1-12 ,
DOI : 10.1007/s11554-010-0169-2
URL : https://hal.archives-ouvertes.fr/hal-00560026
A compiler for hp vee REFERENCES [34 Exploring the concurrency of an MPEG RVC decoder based on dataflow program analysis. Circuits and Systems for Video Technology, Hewlett Packard Journal IEEE Transactions on, vol.49, issue.11, pp.98-99, 1998. ,
Information Technology -MPEG systems technologies -Part 4: Codec Configuration Representation, 2009. ,
Information Technology -MPEG video technologies -Part 4: Video tool library, pp.23002-23006, 2009. ,
Notes on an actor language, 7th Ptolemy Miniconference, 2007. ,
Synthesizing Hardware from Dataflow Programs, Journal of Signal Processing Systems, vol.83, issue.5, pp.1-9 ,
DOI : 10.1007/s11265-009-0397-5
Reconfigurable video coding a stream programming approach to the specification of new video coding standards, MMSys '10: Proceedings of the first annual ACM SIGMM conference on Multimedia systems, pp.223-234, 2010. ,
A dataflow description of acc-jpeg coder, Accepted for the proceedings of 2012 International Conference on Signal Processing and Multimedia Application, 2012. ,
Automatic generation of synthesizable hardware implementation from high level RVC-CAL design, ICASSP'12: Proceedings of the 37th International Conference on Acoustics Speech and Signal Processing, pp.1597-1600, 2012. ,
Design of an Embedded Low Complexity Image Coder using CAL language, 2009. ,
URL : https://hal.archives-ouvertes.fr/hal-00440484
Automatic method for efficient hardware implementation from RVC-CAL dataflow: A lar coder baseline case study, Journal Of Convergence, vol.1, issue.12, pp.85-92 ,
URL : https://hal.archives-ouvertes.fr/hal-00546742
Fast Hardware Implementation of an Hadamard Transform Using RVC-CAL Dataflow Programming, 2010 5th International Conference on Embedded and Multimedia Computing, p.2010 ,
DOI : 10.1109/EMC.2010.5575731
URL : https://hal.archives-ouvertes.fr/hal-00502234
Automatic generation of optimized and synthesizable hardware implementation from high level dataflow programs. VLSI Design, pp.14-2012, 2012. ,
URL : https://hal.archives-ouvertes.fr/hal-00724403
The Semantics of a Simple Language for Parallel Programming ,
Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp.45-56, 2006. ,
DOI : 10.1109/FCCM.2006.28
Synchronous data flow, Proceedings of the IEEE, pp.1235-1245, 1987. ,
DOI : 10.1109/PROC.1987.13876
A denotational semantics for dataflow with firing, 1997. ,
Dataflow process networks, Proceedings of the IEEE, pp.773-801, 1995. ,
The spatial tuning of chromatic mechanisms identified by simultaneous masking, Vision Research, vol.34, issue.3, pp.331-341, 1994. ,
DOI : 10.1016/0042-6989(94)90091-4
MPEG Reconfigurable Video Coding, Handbook of Signal Processing Systems, pp.43-67, 2010. ,
DOI : 10.1007/978-1-4419-6345-1_3
URL : https://hal.archives-ouvertes.fr/hal-00566149
Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking, 2009 International Conference on Computer Technology and Development, pp.535-539, 2009. ,
DOI : 10.1109/ICCTD.2009.195
System-level design merits a closer look: the complexity of today's designs requires system-level design, but EDA-tools development is lagging behind the needs of semiconductor and system companies, EDA tools must support system-level design. (design feature). Electronics Design Strategy, News (EDN), 2002. ,
A functional language for generating structured text, 2006. ,
Enforcing strict model-view separation in template engines, Proceedings of the 13th conference on World Wide Web , WWW '04, pp.224-233, 2004. ,
DOI : 10.1145/988672.988703
Towards compilation of streaming programs into FPGA hardware, 2008 Forum on Specification, Verification and Design Languages, pp.67-72, 2008. ,
DOI : 10.1109/FDL.2008.4641423
Utilisation de la transformation de hadamard pour le codage et la compression de signaux d'images, Springer-Annals of telecommunications, pp.235-252, 1971. ,
Some practical universal noiseless coding techniques, 1979. ,
Hardware-software cosynthesis for digital systems, IEEE Design & Test of Computers, vol.10, issue.3, pp.29-41, 1993. ,
DOI : 10.1109/54.232470
Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study, 2008 IEEE Workshop on Signal Processing Systems, pp.281-286, 2008. ,
DOI : 10.1109/SIPS.2008.4671776
URL : https://hal.archives-ouvertes.fr/hal-00336516
Automatic software synthesis of dataflow program: An MPEG-4 Simple Profile decoder case study, Proceedings of 2008 IEEE Workshop on Signal Processing Systems, pp.281-286, 2008. ,
URL : https://hal.archives-ouvertes.fr/hal-00336516
Managing the Development of Large Software Systems, IEEE proceedings, pp.1-9, 1970. ,
A Practical Introduction to Hardware/Software Codesign, 2010. ,
Optimal quadtree construction algorithms, Computer Vision, Graphics, and Image Processing, vol.37, issue.3, pp.402-419, 1987. ,
Global sales report 2011: http://www.siaonline.org/news/2012/02/06/global-sales-report-2012/semiconductor- industry-posts-record-breaking-revenues-despite-2011-challenges, 2012. ,
Hardware code generation from dataflow programs, 2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), pp.113-120, 2010. ,
DOI : 10.1109/DASIP.2010.5706254
URL : https://hal.archives-ouvertes.fr/hal-00565300
Tree-structured scene adaptive coder, IEEE Transactions on Communications, vol.38, issue.4, pp.477-486, 1990. ,
DOI : 10.1109/26.52659
On-Line Graphical Specification Of Computer Procedures, 1966. ,
Orientation and spatial-frequency discrimination for luminance and chromatic gratings, Journal of the Optical Society of America A, vol.7, issue.6 ,
DOI : 10.1364/JOSAA.7.001034
Constant propagation with conditional branches, ACM Transactions on Programming Languages and Systems, vol.13, issue.2, pp.181-210, 1991. ,
DOI : 10.1145/103135.103136
Software Code Generation for the RVC-CAL Language, Journal of Signal Processing Systems, vol.29, issue.12, 2009. ,
DOI : 10.1007/s11265-009-0390-z
URL : https://hal.archives-ouvertes.fr/hal-00407950
Code generation for the MPEG Reconfigurable Video Coding framework: From CAL actions to C functions, 2008 IEEE International Conference on Multimedia and Expo, pp.1049-1052, 2008. ,
DOI : 10.1109/ICME.2008.4607618
URL : https://hal.archives-ouvertes.fr/hal-00336487
Compilation Infrastructure of Dataflow Programs, 2010. ,
Software Code Generation for the RVC-CAL Language, Journal of Signal Processing Systems, vol.29, issue.12, pp.203-213, 2011. ,
DOI : 10.1007/s11265-009-0390-z
URL : https://hal.archives-ouvertes.fr/hal-00407950
Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs, Signal Processing Image Communication, Special issue on Reconfigurable Video Coding, 2013. ,
DOI : 10.1016/j.image.2013.08.013
URL : https://hal.archives-ouvertes.fr/hal-00909325