S. Il-existe-un-arc, alors le poid de cet arc est fixé égal à la somme des poids de ces arcs. De plus, durant les niveaux successifs de contraction

. Le, expression du chromosome (génotype), Facteur N

M. A. Abido, A new multiobjective evolutionary algorithm for environmental/economic power dispatch, 2001 Power Engineering Society Summer Meeting. Conference Proceedings (Cat. No.01CH37262), p.205, 2001.
DOI : 10.1109/PESS.2001.970254

K. Agarwal, K. Nowka, H. Deogun, and D. Sylvester, Power Gating with Multiple Sleep Modes, 7th International Symposium on Quality Electronic Design (ISQED'06), pp.633-637, 2006.
DOI : 10.1109/ISQED.2006.102

A. Andrei, P. Eles, Z. Peng, M. Schmitz, and B. Hashimi, Energy optimization of multiprocessor systems on chip by voltage selection. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.15, issue.3, pp.262-275, 2007.

G. Ascia, V. Catania, and M. Palesi, Multi-objective mapping for mesh-based NoC architectures, Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , CODES+ISSS '04, pp.182-187, 2004.
DOI : 10.1145/1016720.1016765

D. R. Avresky, C. M. Cunningham, and H. Ravichandran, Fault-tolerant adaptive routing for two-dimensional meshes, Int. Journal of Computer Systems Science and Engineering, vol.14, issue.6, p.132, 1999.

H. Aydin and D. Zhu, Reliability-aware energy management for periodic real-time tasks. Computers, IEEE Transactions on, vol.58, issue.10, pp.1382-1397, 2009.

E. Beigne, F. Clermidy, S. Miermont, and P. Vivet, Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), pp.129-138, 2008.
DOI : 10.1109/NOCS.2008.4492732

J. F. Benders, Partitioning procedures for solving mixed-variables programming problems, pp.238-252, 1962.

L. Benini, D. Bertozzi, A. Guerri, and M. Milano, Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs, Procs. of CPAIOR-2006, pp.44-58, 2006.
DOI : 10.1007/11757375_6

L. Benini, D. Bertozzi, A. Guerri, M. Milano, F. Poletti et al., Measuring efficiency and executability of allocation and scheduling in multi-processor systems-on-chip Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems, GLS '97 : Proceedings of the 7th Great Lakes Symposium on VLSI, pp.13-20, 1997.

S. Borkar, T. Karnik, and V. De, Design and reliability challenges in nanometer technologies, Proceedings of the 41st annual conference on Design automation , DAC '04, pp.75-75, 2004.
DOI : 10.1145/996566.996588

S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi et al., Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation , DAC '03, pp.338-342, 2003.
DOI : 10.1145/775832.775920

K. Bowman, B. Austin, J. Eble, X. Tang, and J. Meindl, A physical alpha-power law mosfet model, Low Power Electronics and Design Proceedings. 1999 International Symposium on, pp.218-222, 1999.

K. A. Bowman, S. G. Duvall, and J. D. , Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration. Solid-State Circuits, IEEE Journal, vol.37, issue.2, pp.183-190, 0191.

F. Buschmann, R. Meunier, H. Rohnert, P. Sommerlad, and M. Stal, Pattern-oriented software architecture : a system of patterns, p.144, 1996.

B. Calhoun and A. Chandrakasan, Ultra-dynamic voltage scaling using sub-threshold operation and local voltage dithering in 90nm cmos. Solid-State Circuits Conference, Digest of Technical Papers. ISSCC. 2005 IEEE International, pp.300-599, 2005.

F. Chaix, D. Avresky, N. Zergainoh, and M. Nicolaidis, Fault-Tolerant Deadlock-Free Adaptive Routing for Any Set of Link and Node Failures in Multi-cores Systems, 2010 Ninth IEEE International Symposium on Network Computing and Applications, pp.52-59, 2010.
DOI : 10.1109/NCA.2010.14

URL : https://hal.archives-ouvertes.fr/hal-00544568

F. Chaix, D. Avresky, N. Zergainoh, and M. Nicolaidis, A fault-tolerant deadlockfree adaptive routing for on chip interconnects, Design, Automation Test in Europe Conference Exhibition (DATE), pp.1-4, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00671500

M. Chen, H. Huang, C. Hou, and K. Yang, Back-gate bias enhanced bandto-band tunneling leakage in scaled mosfet's. Electron Device Letters, pp.134-136, 1998.

Y. Cheng, M. Jeng, Z. Liu, J. Huang, M. Chan et al., A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation, IEEE Transactions on Electron Devices, vol.44, issue.2, pp.277-287, 1997.
DOI : 10.1109/16.557715

C. Chou and R. Marculescu, Run-time task allocation considering user behavior in embedded multiprocessor networks-on-chip. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.29, issue.1, pp.78-91, 2010.

C. Chou, U. Ogras, and R. Marculescu, Energy-and performance-aware incremental mapping for networks on chip with multiple voltage levels. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.27, issue.10, pp.1866-1879, 2008.

C. Coello and G. Pulido, A Micro-Genetic Algorithm for Multiobjective Optimization, Evolutionary Multi-Criterion Optimization, pp.126-140, 1993.
DOI : 10.1007/3-540-44719-9_9

C. A. Coello, A Comprehensive Survey of Evolutionary-Based Multiobjective Optimization Techniques, Knowledge and Information Systems, vol.265, issue.2, pp.129-156, 1999.
DOI : 10.1007/BF03325101

T. H. Cormen, C. Stein, R. L. Rivest, and C. E. Leiserson, Introduction to Algorithms, p.196, 2001.

D. Corne, J. D. Knowles, and M. J. Oates, The pareto envelope-based selection algorithm for multi-objective optimisation, Proceedings of the 6th International Conference on Parallel Problem Solving from Nature, PPSN VI, pp.839-848, 2000.

D. W. Corne, N. R. Jerram, J. D. Knowles, M. J. Oates, and J. Martin, PESA-II : Regionbased Selection in Evolutionary Multiobjective Optimization, Proceedings of the Genetic and Evolutionary Computation Conference (GECCO'2001, pp.283-290, 2001.

N. A. Cressie, Statistics for spatial data, p.187, 1993.

C. M. Cunningham and D. R. Avresky, Fault-tolerant adaptive routing for twodimensional meshes, HPCA '95 : Proceedings of the 1st IEEE Symposium on High- Performance Computer Architecture, p.132, 1995.

S. Das, S. Pant, D. Roberts, S. Lee, D. Blaauw et al., A self-tuning dvs processor using delay-error detection and correction. VLSI Circuits, Digest of Technical Papers. 2005 Symposium on, pp.258-261, 2005.

K. Deb, Multi-Objective Optimization Using Evolutionary Algorithms, p.214, 2001.

K. Deb and D. E. Goldberg, An Investigation of Niche and Species Formation in Genetic Function Optimization, Proceedings of the 3rd International Conference on Genetic Algorithms, pp.42-50, 1989.

K. Deb, A. Pratap, S. Agarwal, and T. Meyarivan, A fast and elitist multiobjective genetic algorithm: NSGA-II, IEEE Transactions on Evolutionary Computation, vol.6, issue.2, pp.182-197, 2002.
DOI : 10.1109/4235.996017

R. P. Dick and N. K. Jha, Mogac : a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems Tgff : task graphs for free, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, ICCAD '97 Proceedings of the 6th international workshop on Hardware/software codesign, CODES/CASHE '98, pp.522-529, 1997.

M. Drosg, Frequency and Probability Distributions, Dealing with Uncertainties, pp.51-69, 2007.
DOI : 10.1007/978-3-642-01384-3_5

D. Ernst, S. Das, S. Lee, D. Blaauw, T. Austin et al., Razor: circuit-level correction of timing errors for low-power operation, IEEE Micro, vol.24, issue.6, pp.2410-2430, 0179.
DOI : 10.1109/MM.2004.85

M. F. Emnett, Power reduction through rtl clock gating, p.174, 2000.

C. Fonseca and P. Fleming, Multiobjective genetic algorithms In Genetic Algorithms for Control Systems Engineering, IEE Colloquium on, vol.5, pp.6-7, 1993.

P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey et al., Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization, Sixth International Symposium on Quality of Electronic Design (ISQED'05), pp.516-521, 2005.
DOI : 10.1109/ISQED.2005.82

M. R. Garey and D. S. Johnson, Computers and Intractability : A Guide to the Theory of NP-Completeness (Series of Books in the Mathematical Sciences, p.36, 1979.

S. Gheorghita, S. Stuijk, T. Basten, and H. Corporaal, Automatic scenario detection for improved WCET estimation, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.101-104, 2005.
DOI : 10.1145/1065579.1065610

S. V. Gheorghita, T. Basten, and H. Corporaal, Intra-task scenario-aware voltage scheduling, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems , CASES '05, pp.177-184, 2005.
DOI : 10.1145/1086297.1086321

D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning

D. E. Goldberg and J. Richardson, Genetic algorithms with sharing for multimodal function optimization, Proceedings of the Second International Conference on Genetic Algorithms on Genetic algorithms and their application, pp.41-49, 1987.

R. Gonzalez, B. Gordon, and M. Horowitz, Supply and threshold voltage scaling for low power cmos. Solid-State Circuits, IEEE Journal, vol.32, issue.169, pp.1210-1216, 1997.

B. Gorjiara, N. Bagherzadeh, and P. Chou, An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes, Proceedings of the 2004 international symposium on Low power electronics and design , ISLPED '04, pp.381-386, 2004.
DOI : 10.1145/1013235.1013326

T. Grandpierre and Y. Sorel, From algorithm and architecture specifications to automatic generation of distributed real-time executives: a seamless flow of graphs transformations, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings., p.50, 2003.
DOI : 10.1109/MEMCOD.2003.1210097

P. Hajela and C. Y. Lin, Genetic search strategies in multicriterion optimal design. Structural and Multidisciplinary Optimization, pp.99-107, 1007.

P. Hoang and J. Rabaey, Scheduling of DSP programs onto multiprocessors for maximum throughput, IEEE Transactions on Signal Processing, vol.41, issue.6, pp.2225-2235, 1993.
DOI : 10.1109/78.218149

J. Horn, N. Nafpliotis, and D. Goldberg, A niched Pareto genetic algorithm for multiobjective optimization, Proceedings of the First IEEE Conference on Evolutionary Computation. IEEE World Congress on Computational Intelligence, pp.82-87, 0205.
DOI : 10.1109/ICEC.1994.350037

J. Hu and R. Marculescu, Energy-and performance-aware mapping for regular noc architectures . Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions, vol.24, issue.4, pp.551-562, 2005.

M. Hwang, T. Cakici, and K. Roy, Interactive presentation : Process tolerant ?-ratio modulation for ultra-dynamic voltage scaling, DATE '07 : Proceedings of the conference on Design, automation and test in Europe, pp.1550-1555, 2007.

M. H. Yasuura and T. Ishihara, Energy Management Techniques for SOC Design, pp.177-223, 2006.
DOI : 10.1007/1-4020-5352-5_6

V. Izosimov, P. Pop, P. Eles, and Z. Peng, Synthesis of Fault-Tolerant Schedules with Transparency/Performance Trade-offs for Distributed Embedded Systems, Proceedings of the Design Automation & Test in Europe Conference, pp.1-6, 2006.
DOI : 10.1109/DATE.2006.244067

H. Jingcao and R. Marculescu, Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.234-239, 2004.
DOI : 10.1109/DATE.2004.1268854

P. Juang, Q. Wu, L. Peh, M. Martonosi, and D. W. Clark, Coordinated, distributed, formal energy management of chip multiprocessors, Proceedings of the 2005 international symposium on Low power electronics and design , ISLPED '05, pp.127-130, 2005.
DOI : 10.1145/1077603.1077637

A. Kahng, How much variability can designers tolerate. Design and Test of Computers, IEEE, vol.20, issue.6, pp.96-97, 0189.

K. Kanda, K. Nose, H. Kawaguchi, T. Sakurai, T. Karnik et al., Design impact of positive temperature dependence of drain current in sub 1 v cmos vlsis. Custom Integrated Circuits Probabilistic and variation-tolerant design : Key to continued moore ?s law, Proceedings of the IEEE 1999 Proc. Workshop Timing Issues in Specification Synthesis Digital Systems, pp.563-566, 1999.

G. Karypis and V. Kumar, Parallel multilevel k-way partitioning scheme for irregular graphs, Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) , Supercomputing '96, 0200.
DOI : 10.1145/369028.369103

G. Karypis and V. Kumar, A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs, SIAM Journal on Scientific Computing, vol.20, issue.1, pp.359-392, 0201.
DOI : 10.1137/S1064827595287997

G. Karypis and V. Kumar, Multilevel Algorithms for Multi-Constraint Graph Partitioning, Proceedings of the IEEE/ACM SC98 Conference, pp.1-13, 0200.
DOI : 10.1109/SC.1998.10018

G. Karypis and V. Kumar, Parallel multilevel k-way partitioning scheme for irregular graphs, Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) , Supercomputing '96, pp.96-129, 0201.
DOI : 10.1145/369028.369103

H. Kawaguchi, G. Zhang, S. Lee, and T. Sakurai, An lsi for vdd-hopping and mpeg4 system based on the chip, ISCAS (4), pp.918-921, 2001.

M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low power methodology manual for system-on-chip design, p.175, 2008.

A. Keshavarzi, S. Ma, S. Narendra, B. Bloechel, K. Mistry et al., Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs, Proceedings of the 2001 international symposium on Low power electronics and design , ISLPED '01, pp.207-212, 2001.
DOI : 10.1145/383082.383135

A. Keshavarzi, S. Narendra, S. Borkar, C. Hawkins, K. Royi et al., Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's, Proceedings of the 1999 international symposium on Low power electronics and design , ISLPED '99, pp.252-254, 1999.
DOI : 10.1145/313817.313937

A. Keshavarzi, G. Schrom, S. Tang, S. Ma, K. Bowman et al., Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltage, Proceedings of the 2005 international symposium on Low power electronics and design , ISLPED '05, pp.26-29, 0189.
DOI : 10.1145/1077603.1077611

N. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner et al., Leakage current : Moore's law meets static power, Computer, issue.12, pp.3668-75, 2003.

J. Knowles and D. Corne, The Pareto archived evolution strategy: a new baseline algorithm for Pareto multiobjective optimisation, Proceedings of the 1999 Congress on Evolutionary Computation-CEC99 (Cat. No. 99TH8406), p.213, 1999.
DOI : 10.1109/CEC.1999.781913

J. D. Knowles and D. W. Corne, Approximating the Nondominated Front Using the Pareto Archived Evolution Strategy, Evolutionary Computation, vol.8, issue.2, pp.149-172, 0205.
DOI : 10.1109/4235.797969

A. Konak, D. W. Coit, and A. E. Smith, Multi-objective optimization using genetic algorithms: A tutorial, Reliability Engineering & System Safety, vol.91, issue.9, pp.992-1007, 0207.
DOI : 10.1016/j.ress.2005.11.018

F. Kursawe, A variant of evolution strategies for vector optimization, Parallel Problem Solving from Nature, pp.193-197, 0208.
DOI : 10.1007/BFb0029752

S. Lee and T. Sakurai, Run-time voltage hopping for low-power real-time systems, Proceedings of the 37th conference on Design automation , DAC '00, pp.806-809, 2000.
DOI : 10.1145/337292.337785

H. Li, S. Bhunia, Y. Chen, T. N. Vijaykumar, and K. Roy, Deterministic clock gating for microprocessor power reduction, HPCA '03 : Proceedings of the 9th International Symposium on High-Performance Computer Architecture, pp.113-174, 2003.

Q. Li, Y. Ruan, T. Shidayang, and . Jiang, An Optimal Scheduling Algorithm for Fork-Join Task Graphs, Journal of Software, vol.16, issue.5, pp.587-589, 2003.
DOI : 10.1360/jos160684

Y. Lin, M. Kudlur, S. Mahlke, and T. Mudge, Hierarchical coarse-grained stream compilation for software defined radio, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems , CASES '07, pp.115-124, 2007.
DOI : 10.1145/1289881.1289903

X. Liu and S. Mourad, Performance of submicron CMOS device and logic gates with substrate biasing, Microelectronic Device Technology III, pp.9-12, 2000.
DOI : 10.1117/12.360545

Z. Liu, C. Hu, J. Huang, T. Chan, M. Jeng et al., Threshold voltage model for deep-submicrometer MOSFETs, IEEE Transactions on Electron Devices, vol.40, issue.1, pp.86-95, 0168.
DOI : 10.1109/16.249429

H. Lu and G. Yen, Rank-density-based multiobjective genetic algorithm and benchmark test function study, Evolutionary Computation IEEE Transactions on, vol.7, issue.209, pp.325-343, 2003.

J. Luo and N. K. Jha, Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, ICCAD '00, pp.357-364, 2000.

Y. Luo, J. Yu, J. Yang, and L. Bhuyan, Low power network processor design using clock gating, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.712-715, 2005.
DOI : 10.1145/1065579.1065766

Z. Ma, P. Marchal, D. P. Scarpazza, P. Yang, C. Wong et al., Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms, p.94, 2007.

S. Martin, K. Flautner, T. Mudge, and D. Blaauw, Combined dynamic voltage scaling and adaptive body biasing for lower power microprocessors under dynamic workloads

S. Miermont, P. Vivet, and M. Renaudin, A power supply selector for energy-and areaefficient local dynamic voltage scaling, PATMOS, pp.556-565, 2007.

B. Min, A. Andrei, P. Eles, and P. Zebo, On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration, Design Automation Conference DAC '09, pp.490-495, 2009.

F. Muhammad, F. Muller, and M. Auguin, Contentions-conscious dynamic but deterministic scheduling of computational and communication tasks, Proceedings of the 2006 ACM symposium on Applied computing , SAC '06, pp.1487-1492, 2006.
DOI : 10.1145/1141277.1141623

URL : https://hal.archives-ouvertes.fr/hal-00525035

T. Murata and H. Ishibuchi, MOGA: multi-objective genetic algorithms, Proceedings of 1995 IEEE International Conference on Evolutionary Computation, pp.289-290, 1995.
DOI : 10.1109/ICEC.1995.489161

T. Murata, H. Ishibuchi, and H. Tanaka, Multi-objective genetic algorithm and its applications to flowshop scheduling, Computers & Industrial Engineering, vol.30, issue.4, pp.957-968, 0208.
DOI : 10.1016/0360-8352(96)00045-9

B. Nam, J. Lee, K. Kim, S. J. Lee, and H. Yoo, A 52.4mw 3d graphics processor with 141mvertices/s vertex shader and 3 power domains of dynamic voltage and frequency scaling. Solid-State Circuits Conference, Digest of Technical Papers. IEEE International, pp.278-603, 2007.

B. Nam, J. Lee, K. Kim, S. J. Lee, and H. Yoo, A low-power handheld gpu using logarithmic arithmetic and triple dvfs power domains Eurographics Association, GH '07 : Proceedings of the 22nd ACM SIGGRAPH/EUROGRAPHICS symposium on Graphics hardware, pp.73-80, 2007.

N. Ranaldo and E. Zimeo, An economy-driven mapping heuristic for hierarchical masterslave applications in grid systems, Parallel and Distributed Processing Symposium, p.144, 2006.

P. J. Ribeiro and P. Diggle, geor : A package for geostatistical analysis, p.188, 2001.

K. Roy, S. Mukhopadhyay, and H. Mahmoodi-meimand, Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits, Proceedings of the IEEE, vol.91, issue.2, pp.305-327, 2003.
DOI : 10.1109/JPROC.2002.808156

T. Sakurai and R. Newton, Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas, IEEE Journal of Solid-State Circuits, vol.25, issue.2, 0190.
DOI : 10.1109/4.52187

S. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A. Tiwari et al., Varius : A model of process variation and resulting timing errors for microarchitects. Semiconductor Manufacturing, IEEE Transactions on, vol.21, issue.186, pp.3-13, 2008.

T. Sato and Y. Kunitake, A Simple Flip-Flop Circuit for Typical-Case Designs for DFM, 8th International Symposium on Quality Electronic Design (ISQED'07), pp.539-544, 2007.
DOI : 10.1109/ISQED.2007.23

J. D. Schaffer, Multiple objective optimization with vector evaluated genetic algorithms, Proceedings of the 1st International Conference on Genetic Algorithms, pp.93-100, 1985.

S. Segars, K. Clarke, and L. Goudge, Embedded control problems, Thumb, and the ARM7TDMI, IEEE Micro, vol.15, issue.5, pp.22-30, 1995.
DOI : 10.1109/40.464580

G. Semeraro, D. H. Albonesi, S. G. Dropsho, G. Magklis, S. Dwarkadas et al., Dynamic frequency and voltage control for a multiple clock domain microarchitecture, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings., pp.356-367, 2002.
DOI : 10.1109/MICRO.2002.1176263

G. Semeraro, G. Magklis, R. Balasubramonian, D. H. Albonesi, S. Dwarkadas et al., Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling, Proceedings Eighth International Symposium on High Performance Computer Architecture, pp.29-177, 2002.
DOI : 10.1109/HPCA.2002.995696

G. Shao, F. Berman, and R. Wolski, Master/slave computing on the Grid, Proceedings 9th Heterogeneous Computing Workshop (HCW 2000) (Cat. No.PR00556), pp.3-16, 2000.
DOI : 10.1109/HCW.2000.843728

D. Shin and J. Kim, Power-aware scheduling of conditional task graphs in real-time multiprocessor systems, Proceedings of the 2003 international symposium on Low power electronics and design , ISLPED '03, pp.408-413, 2003.
DOI : 10.1145/871506.871607

Y. Shin, S. Chae, and K. Choi, Partial bus-invert coding for power optimization of system level bus, Proceedings of the 1998 international symposium on Low power electronics and design , ISLPED '98, pp.127-129, 1998.
DOI : 10.1145/280756.280829

N. Srinivas and K. Deb, Muiltiobjective Optimization Using Nondominated Sorting in Genetic Algorithms, Evolutionary Computation, vol.27, issue.3, pp.221-248, 1994.
DOI : 10.1162/evco.1994.2.3.221

A. Srivastava, D. Sylvester, and D. Blaauw, Statistical analysis and optimization for vlsi : Timing and power, p.187, 2005.

M. Stan, Optimal voltages and sizing for low power [CMOS VLSI], Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013), pp.428-433, 0170.
DOI : 10.1109/ICVD.1999.745193

M. R. Stan and W. P. Burleson, Bus-invert coding for low-power i/o. IEEE Trans. Very Large Scale Integr Analysis and decomposition of spatial variation in integrated circuit processes and devices, Syst. IEEE Transactions on Semiconductor Manufacturing, vol.3, issue.10, pp.49-58, 1995.

C. Su, C. Tsui, and A. Despain, Low power architecture design and compilation techniques for high-performance processors. Compcon Spring '94, Digest of Papers, pp.489-498, 1994.

V. Suhendra, C. Raghavan, and T. Mitra, Integrated scratchpad memory optimization and task scheduling for MPSoC architectures, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems , CASES '06, pp.401-410, 2006.
DOI : 10.1145/1176760.1176809

Y. Taur and T. H. Ning, Fundamentals of modern VLSI devices, p.184, 1998.

R. Teodorescu, J. Nakano, A. Tiwari, and J. Torrellas, Mitigating parameter variation with dynamic fine-grain body biasing. Microarchitecture, MICRO 2007. 40th Annual IEEE/ACM International Symposium on, pp.27-42, 0193.

D. A. Van-veldhuizen and G. B. Lamont, Multiobjective Evolutionary Algorithms: Analyzing the State-of-the-Art, Evolutionary Computation, vol.8, issue.2, pp.125-147, 0214.
DOI : 10.1109/4235.797969

G. Varatkar and R. Marculescu, Communication-aware task scheduling and voltage selection for total systems energy minimization, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486), pp.510-517, 2003.
DOI : 10.1109/ICCAD.2003.159732

H. Veendrick, Short-circuit dissipation of static cmos circuitry and its impact on the design of buffer circuits. Solid-State Circuits, IEEE Journal, vol.19, issue.4, pp.468-473, 1984.

Q. Wu, P. Juang, M. Martonosi, and D. W. Clark, Formal online methods for voltage/frequency control in multiple clock domain microprocessors, ACM SIGPLAN Notices, vol.39, issue.11, pp.248-259, 2004.
DOI : 10.1145/1037187.1024423

Q. Wu, M. Pedram, and X. Wu, Clock-gating and its application to low power design of sequential circuits. Custom Integrated Circuits Conference, Proceedings of the IEEE 1997, pp.479-482, 0174.

J. Xiong, V. Zolotov, and L. He, Robust extraction of spatial correlation, ISPD '06 : Proceedings of the 2006 international symposium on Physical design, pp.2-9, 2006.

P. Yang and F. Catthoor, Pareto-optimization-based run-time task scheduling for embedded systems, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis , CODES+ISSS '03, pp.120-125, 2003.
DOI : 10.1145/944645.944680

T. Ye, L. Benini, and G. Micheli, Analysis of power consumption on switch fabrics in network routers, Design Automation Conference Proceedings. 39th, pp.524-529, 2002.

G. Yen and H. Lu, Dynamic multiobjective evolutionary algorithm: adaptive cell-based rank and density estimation, IEEE Transactions on Evolutionary Computation, vol.7, issue.3, pp.253-274, 2003.
DOI : 10.1109/TEVC.2003.810068

Y. Yoshida, B. Song, H. Okuhata, T. Onoye, and I. Shirakawa, An object code compression approach to embedded processors, Proceedings of the 1997 international symposium on Low power electronics and design , ISLPED '97, pp.265-268, 1997.
DOI : 10.1145/263272.263349

H. Yu, B. Veeravalli, and Y. Ha, Leakage-aware dynamic scheduling for real-time adaptive applications on multiprocessor systems, Proceedings of the 47th Design Automation Conference on, DAC '10, pp.47-493, 2010.
DOI : 10.1145/1837274.1837396

Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan, Hotleakage : A temperature-aware model of subthreshold and gate leakage for architects, 0191.

B. Zhao, H. Aydin, and D. Zhu, Reliability-aware dynamic voltage scaling for energyconstrained real-time embedded systems, Computer Design IEEE International Conference on, pp.633-639, 2008.

B. Zhao, H. Aydin, and D. Zhu, Enhanced reliability-aware power management through shared recovery technique, Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD '09, pp.63-70, 2009.
DOI : 10.1145/1687399.1687412

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.221.4064

H. C. Zhao, C. H. Xia, Z. Liu, and D. Towsley, A unified modeling framework for distributed resource allocation of general fork and join processing networks, ACM SIGMETRICS Performance Evaluation Review, vol.38, issue.1, pp.299-310, 2010.
DOI : 10.1145/1811099.1811073

E. Zitzler, K. Deb, and L. Thiele, Comparison of Multiobjective Evolutionary Algorithms: Empirical Results, Evolutionary Computation, vol.8, issue.2, pp.173-195, 0205.
DOI : 10.1109/4235.797969

E. Zitzler, M. Laumanns, and L. Thiele, SPEA2 : Improving the Strength Pareto Evolutionary Algorithm, pp.8092-211, 2001.

E. Zitzler and L. Thiele, Multiobjective evolutionary algorithms: a comparative case study and the strength Pareto approach, IEEE Transactions on Evolutionary Computation, vol.3, issue.4, pp.257-271, 1999.
DOI : 10.1109/4235.797969

P. Personnelles, ?. Gilles-bizot, and D. Avresky, Fabien Chaix, Nacer-Eddine Zergainoh, and Michael Nicolaidis . Self-recovering parallel applications in multi-core systems, Network Computing and Applications (NCA), 10th IEEE International Symposium on, pp.51-58, 2011.

?. Gilles-bizot, N. Zergainoh, and M. Nicolaidis, Variability and reliabilityaware application tasks scheduling and power control (voltage and frequency scaling) in the future nanoscale multiprocessors system on chip, On-Line Testing Symposium, IOLTS. 15th IEEE International, p.155, 2009.

?. Gilles-bizot, D. Avresky, F. Chaix, N. Zergainoh, and M. Nicolaidis, Adaptive mapping of parallelized application (fork-join dag) on multicore system in the presence of multiple failures, 17th IEEE Workshop on Dependable Parallel, Distributed and Network-Centric Systems (DPDNS), 2012.

?. Gilles-bizot, N. Zergainoh, and M. Nicolaidis, Energy and variability aware scheduling for clusterized mpsoc architecture, 2nd IEEE Design for Reliability and Variability (DRVW), 2009.

?. Fabien-chaix, G. Bizot, M. Nicolaidis, and N. Zergainoh, Variabilityaware task mapping strategies for many-cores processor chips, On-Line Testing Symposium (IOLTS), IEEE 17th International, pp.55-60, 2011.

?. Fabien-chaix, G. Bizot, M. Nicolaidis, and N. Zergainoh, Variabilityaware task mapping strategies for many-cores processor chips, 4th IEEE Design for Reliability and Variability Workshop (DRVW), 2011.

. Mpsoc, NoC, variabilité, placement, ordonnancement, tolérance aux fautes, faible consommation d'énergie