J. Agron, Domain-Specific Language for HW/SW Co-design for FPGAs. DSL, pp.262-284, 2009.

K. Akesson, M. Fabian, and H. Flordal, Supremica in a Nutshell ? Draft

K. Akesson, M. Fabian, H. Flordal, and R. Malik, Supremica - An integrated environment for verification, synthesis and simulation of discrete event systems, 2006 8th International Workshop on Discrete Event Systems, pp.384-385, 2006.
DOI : 10.1109/WODES.2006.382401

K. Altisen, A. Clodic, F. Maraninchi, and É. Rutten, Using Controller-Synthesis Techniques to Build Property-Enforcing Layers, volume 2618 of Lecture Notes in Computer Science, 2003.

D. Amos, A. Lesea, and R. Richter, FPGA-Based Prototyping Methodology Manual. Best Practices in Design-For-Prototyping, 2011.

X. An, S. Boumedien, A. Gamatié, and É. Rutten, CLASSY, Proceedings of the 15th International Workshop on Software and Compilers for Embedded Systems, SCOPES '12, 2012.
DOI : 10.1145/2236576.2236577

URL : https://hal.archives-ouvertes.fr/hal-00758194

C. André, Representation and analysis of reactive behaviors : A synchronous approach, Computational Engineering in Systems Applications (CESA), pp.19-29, 1996.

R. Back and K. Sere, From action systems to modular systems . FME'94 : Industrial Benefit of Formal Methods, 1994.

K. Beck, Extreme Programming Explained : Embrace Change, 1999.

K. Beck, Test Driven Development : By Example, 2002.

K. Benkrid, A. Akoglu, C. Ling, Y. Song, Y. Liu et al., High Performance Biological Pairwise Sequence Alignment: FPGA versus GPU versus Cell BE versus GPP, International Journal of Reconfigurable Computing, vol.85, issue.8, 2012.
DOI : 10.1093/bioinformatics/btl582

URL : http://doi.org/10.1155/2012/752910

M. Berg, Fault tolerance implementation within SRAM based FPGA designs based upon the increased level of single event upset susceptibility. On-Line Testing Symposium, 2006.

G. Berry, The foundations of Esterel. Proof, Language, and Interaction : Essays in Honour of Robin Milner, pp.425-454, 2000.

B. Blodget, S. Mcmillan, and P. Lysaght, A lightweight approach for embedded reconfiguration of FPGAs, 2003 Design, Automation and Test in Europe Conference and Exhibition, pp.399-400, 2003.
DOI : 10.1109/DATE.2003.1253642

P. Bomel, G. Gogniat, and J. Diguet, A Networked, Lightweight and Partially Reconfigurable Platform, 4th International Workshop, 2008.
DOI : 10.1007/978-3-540-78610-8_35

URL : https://hal.archives-ouvertes.fr/hal-00282224

T. Bouhadiba, Q. Sabah, G. Delaval, and É. Rutten, Synchronous control of reconfiguration in fractal component-based systems -A case study, Proceedings of the International Conference on Embedded Software (EMSOFT), pp.309-318, 2011.
URL : https://hal.archives-ouvertes.fr/inria-00596883

W. Lindsey-buntine and B. Preas, Design rule checking and analysis of IC mask designs, Proceedings of the 13th Design Automation Conference, pp.301-308, 1976.

P. Caspi, G. Hamon, and M. Pouzet, Lucid Synchrone, un langage de programmation des systèmes réactifs, Systèmes Temps-réel : Techniques de Description et de Vérification -Théorie et Outils, pp.217-260, 2006.

S. Cherif, S. Imran-rafiq-quadri, J. Meftali, and . Dekeyser, Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis, 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, pp.706-713, 2010.
DOI : 10.1109/DSD.2010.58

URL : https://hal.archives-ouvertes.fr/inria-00525004

P. Pong and . Chu, FPGA Prototyping by VHDL Examples. Xilinx Spartan-3 Version, 2011.

E. Melson-clarke, E. A. Emerson, and A. P. Sistla, Automatic verification of finite-state concurrent systems using temporal logic specifications, ACM Transactions on Programming Languages and Systems, vol.8, issue.2, pp.244-263, 1986.
DOI : 10.1145/5397.5399

P. C. , P. Coussy, D. Gajski, M. Meredith, and A. Takach, Abstract interpretation An Introduction to High-Level Synthesis, ACM Computing Surveys (CSUR) Design & Test of Computers, vol.24, issue.264, pp.8-17, 1996.

P. Coussy and A. Morawiec, High-Level Synthesis. From Algorithm to Digital Circuit, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00414328

J. Curreri, G. Stitt, and A. George, High-level synthesis techniques for incircuit assertion-based verification. Parallel & Distributed Processing, Workshops and Phd Forum, 2010 IEEE International Symposium on, pp.1-8, 2010.

G. Delaval, Répartition modulaire de programmes synchrones, 2008.

G. Delaval, H. Marchand, and É. Rutten, Contracts for modular discrete controller synthesis, LCTES '10 : Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems, 2010.
URL : https://hal.archives-ouvertes.fr/inria-00436560

L. Devaux, S. Pillement, D. Chillet, and D. Demigny, Os services for reconfigurable system-on-chip communications. Design of Circuits and Integrated Systems, 2010.
URL : https://hal.archives-ouvertes.fr/inria-00536709

J. Diguet, Y. Eustache, and G. Gogniat, Closed-loop based selfadaptive HW/SW embedded systems : design methodology and smart cam case study, ACM Trans. Embed. Comput. Syst, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00457268

A. Dollas, B. Ward, J. D. , and S. Babcock, Lecture Notes in Computer Science, volume 849 of GerhardGoosJurisHartmanisLecture Notes in Computer Science0302-97431611-3349, 2005.

M. Dowty, Test driven development of embedded systems using existing software test infrastructure, 2004.

E. Dumitrescu, A. Girault, H. Marchand, and É. Rutten, Multicriteria optimal reconfiguration of fault-tolerant real-time tasks, Workshop on Discrete Event Systems, pp.366-373
DOI : 10.3182/20100830-3-DE-4013.00059

C. Ebeling, C. Fisher, G. Xing, M. Shen, and H. Liu, Implementing an OFDM receiver on the RaPiD reconfigurable architecture. Computers, IEEE Transactions on, vol.53, issue.11, pp.1436-1448, 2004.

S. Eisenhardt, T. Oppold, T. Schweizer, and W. Rosenstiel, Optimizing Partial Reconfiguration of Multi-context Architectures, 2008 International Conference on Reconfigurable Computing and FPGAs, pp.67-72, 2008.
DOI : 10.1109/ReConFig.2008.21

T. El-ghazawi, E. El-araby, M. Huang, K. Gaj, V. Kindratenko et al., The Promise of High-Performance Reconfigurable Computing, Computer, vol.41, issue.2, pp.69-76, 2008.
DOI : 10.1109/MC.2008.65

G. Estrin, western joint IRE-AIEE-ACM computer conference on -IRE-AIEE-ACM '60 (Western) In Papers presented at the May 3-5, 1960, western joint IRE-AIEE-ACM computer conference, p.33, 1960.

M. Faugère, T. Bourbeau, R. De-simone, and S. Gérard, MARTE: Also an UML Profile for Modeling AADL Applications, 12th IEEE International Conference on Engineering Complex Computer Systems (ICECCS 2007), pp.359-364, 2007.
DOI : 10.1109/ICECCS.2007.29

S. Foroutan, Y. Thonnart, R. Hersemeule, and A. Jerraya, A Markov chain based method for NoC end-to-end latency evaluation, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), pp.1-8, 2010.
DOI : 10.1109/IPDPSW.2010.5470788

A. Gamatié, S. L. Beux, É. Piel, R. Ben-atitallah, A. Etien et al., A Model-Driven Design Framework for Massively Parallel Embedded Systems, ACM Transactions on Embedded Computing Systems, vol.10, issue.4, pp.1-39, 2011.
DOI : 10.1145/2043662.2043663

E. Gamma, Design Patterns. Elements of Reusable Object-Oriented Software, 1995.

C. Glitia, P. Dumont, and P. Boulet, Array-OL with delays, a domain specific specification language for multidimensional intensive signal processing, Multidimensional Systems and Signal Processing, vol.13, issue.6, 2010.
DOI : 10.1007/s11045-009-0085-4

URL : https://hal.archives-ouvertes.fr/inria-00522751

G. Gogniat, J. Vidal, L. Ye, J. Crenne, S. Guillet et al., Self-reconfigurable embedded systems : from modeling to implementation. Engineering of Reconfigurable Systems and Algorithms (ERSA), PipeRench : A Coprocessor for Streaming multimedia Acceleration. ISCA, pp.28-39, 1999.
URL : https://hal.archives-ouvertes.fr/hal-00488577

M. Object and . Group, Meta Object Facility

M. Object and . Group, Model Driven Architecture

M. Object and . Group, Modeling and analysis of real-time and embedded systems (MARTE) [online]

M. Object and . Group, Unified Modeling Language specification

. Gtkwave, Official website [online] URL : http://gtkwave.sourceforge.net

S. Guillet, N. L. Florent-de-lamotte, É. Griguer, J. Rutten, G. Diguet et al., Designing formal reconfiguration control using UML/MARTE, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012.
DOI : 10.1109/ReCoSoC.2012.6322870

URL : https://hal.archives-ouvertes.fr/hal-00747716

S. Guillet, N. L. Florent-de-lamotte, É. Griguer, J. Rutten, G. Diguet et al., Modeling and synthesis of a Dynamic and Partial Reconfiguration controller, 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012.
DOI : 10.1109/FPL.2012.6339157

URL : https://hal.archives-ouvertes.fr/hal-00747718

S. Guillet, É. Florent-de-lamotte, G. Rutten, J. Gogniat, and . Diguet, Modeling and Formal Control of Partial Dynamic Reconfiguration, 2010 International Conference on Reconfigurable Computing and FPGAs, 2010.
DOI : 10.1109/ReConFig.2010.56

URL : https://hal.archives-ouvertes.fr/hal-00663437

S. Guillet and L. Lagadec, Ajout d'un système de types à un atelier de synthèse de circuits, MajecSTIC, 2008.

N. Halbwachs, Synchronous programming of reactive systems, Kluwer Academic, 1993.

N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud, The synchronous data flow programming language LUSTRE, Proceedings of the IEEE, 1991.
DOI : 10.1109/5.97300

D. Harel and A. Naamad, The STATEMATE semantics of statecharts, ACM Transactions on Software Engineering and Methodology, vol.5, issue.4, 1996.
DOI : 10.1145/235321.235322

D. Harel and A. Pnueli, On the development of reactive systems. Logic and Models of Concurrent Systems, 1985.

R. Hartenstein, A decade of reconfigurable computing: a visionary retrospective, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.642-649, 2001.
DOI : 10.1109/DATE.2001.915091

S. Hauck, The future of reconfigurable systems, 5th Canadian Conference on Field Programmable Devices, 1998.

G. Hoffmann and H. Wong-toi, Symbolic synthesis of supervisory controllers, 1992.

W. Howes, On-orbit FPGA SEU Mitigation and Measurement Experiments on the Cibola Flight Experiment Satellite, 2011.

V. Ishakian and A. Bestavros, MORPHOSYS: Efficient Colocation of QoS-Constrained Workloads in the Cloud, 2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012), pp.90-97, 2012.
DOI : 10.1109/CCGrid.2012.44

S. Johnson, Lint, a C program checker, Computer science technical report, 1978.

G. Kahn, The semantics of a simple language for parallel programming, Proceedings of IFIP Congress, 1974.

S. Kent, Model Driven Engineering, volume 2335 of IFM '02, Proceedings of the Third International Conference on Integrated Formal Methods, 2002.

M. Kerboeuf, A. Plantec, and J. Babau, An experiment of a MDE approach for the design of reusable DSL tools, Actes des journées sur l'Ingénierie Dirigée par les Modèles (IDM), pp.25-30, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00631307

M. Koester, W. Luk, J. Hagemeyer, and M. Porrmann, Design optimizations to improve placeability of partial reconfiguration modules, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.976-981, 2009.
DOI : 10.1109/DATE.2009.5090806

W. Kranz, An Integrated System Development Process including Hardware and Logistics based on a Standard Software Process Model. Technology for Evolutionary Software Development, 2003.

E. Kursun and C. Cher, Variation-aware thermal characterization and management of multi-core architectures, 2008 IEEE International Conference on Computer Design, pp.280-285, 2008.
DOI : 10.1109/ICCD.2008.4751874

P. Lacan, J. N. Monfort, L. Vin-quy-ribal, A. Deutsch, and G. Gonthier, ARIANE 5 -The Software Reliability Verification Process, Data Systems in Aerospace, 1998.

L. Lagadec, B. Pottier, and O. Villellas-guillen, An LUT-based high level synthesis framework for reconfigurable architectures. Domain-Specific Processors : Systems, Architectures, Modeling, and Simulation, 2003.

P. Sébastien-le-beux, J. Marquet, and . Dekeyser, Model Driven Engineering Benefits for High Level Synthesis, 2008.

T. Paul-le-guernic, M. L. Gautier, C. L. Borgne, and M. , Programming Real Time Applications with SIGNAL, Proceedings of the IEEE, 1991.

. Gerard-le-lann, The Ariane 5 Flight 501 Failure -A Case Study in System Engineering for Computing Systems, 1996.

S. Lecomte, S. Guillouard, C. Moy, P. Leray, and P. Soulard, A co-design methodology based on model driven architecture for real time embedded systems, Mathematical and Computer Modelling, vol.53, issue.3-4, pp.3-4, 2011.
DOI : 10.1016/j.mcm.2010.03.035

URL : https://hal.archives-ouvertes.fr/hal-00488575

É. Lemoine and D. Merceron, Run time reconfiguration of FPGA for scanning genomic databases, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines, pp.90-98, 1995.
DOI : 10.1109/FPGA.1995.477414

S. Leue and W. Wei, Integer Linear Programming-Based Property Checking for Asynchronous Reactive Systems, IEEE Transactions on Software Engineering, vol.39, issue.2, 2011.
DOI : 10.1109/TSE.2011.1

N. Leveson and C. Turner, An investigation of the Therac-25 accidents, Computer, vol.26, issue.7, pp.18-41, 1993.
DOI : 10.1109/MC.1993.274940

F. Madlener, A. Biedermann, and S. Huss, RecDEVS: A Comprehensive Model of Computation for Dynamically Reconfigurable Hardware Systems, 4th IFAC Workshop on Discrete-Event System Design, 2009.
DOI : 10.3182/20091006-3-ES-4010.00026

F. Maraninchi and Y. Rémond, Mode-automata: About modes and states for reactive systems, European Symposium On Programming, 1998.
DOI : 10.1007/BFb0053571

F. Maraninchi and Y. Rémond, Argos: an automaton-based synchronous language, Computer Languages, vol.27, issue.1-3, 2001.
DOI : 10.1016/S0096-0551(01)00016-9

URL : https://hal.archives-ouvertes.fr/hal-00273055

F. Maraninchi and Y. Rémond, Mode-Automata: a new domain-specific construct for the development of safe critical systems, Science of Computer Programming, vol.46, issue.3, pp.219-254, 2003.
DOI : 10.1016/S0167-6423(02)00093-X

P. Masson, Vérification par model-checking modulaire de propriétés dynamiques PLTL exprimées dans le cadre de spécifications B événementielles, 2001.

J. Mcdermid and K. Ripken, Life cycle support in the Ada environment, ACM SIGAda Ada Letters, vol.III, issue.1, 1983.
DOI : 10.1145/998373.998379

K. Mcmillan, Symbolic Model Checking, an approach to the state explosion problem, 1992.

C. Mead and L. Conway, Introduction to VLSI Systems, 1980.

G. Mealy, A method for synthesizing sequential circuits, The Bell System Technical Journal, vol.34, issue.5, 1955.
DOI : 10.1002/j.1538-7305.1955.tb03788.x

M. Mernik, J. Heering, and A. M. Sloane, When and how to develop domain-specific languages, ACM Computing Surveys, vol.37, issue.4, pp.316-344, 2005.
DOI : 10.1145/1118890.1118892

M. Merten, Design of Interactive Service Robots applying methods of Systems Engineering and Decision Making, 2012.

J. Miller and J. Mukerji, Model driven architecture, 2003.

F. Muller, J. Le-rhun, F. Lemonnier, B. Miramond, and L. Devaux, A Flexible Operating System for Dynamic Applications, Xcell Journal, p.73, 2010.
URL : https://hal.archives-ouvertes.fr/hal-00542646

M. Mura, L. G. Murillo, and M. Prevostini, Model-based Design Space Exploration for RTES with SysML and MARTE. Specification, Verification and Design Languages, Forum on, pp.203-208, 2008.

S. Narayanan and D. Chillet, Sébastien Pillement, and Ioannis Sourdis. Hardware OS Communication Service and Dynamic Memory Management for RSoCs, International Conference on Reconfigurable Computing and FPGAs (ReConFig), pp.117-122, 2011.

G. Ochoa, E. Bourennane, O. Labbani, and K. Messaoudi, IP- XACT and marte based approach for partially reconfigurable systems-on-chip, pp.1-8, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00674293

P. Øhrstrøm and P. Hasle, Temporal Logic : From Ancient Ideas to Artificial Intelligence. Studies in Linguistics and Philosophy, 1995.

O. Pell, Verification of FPGA Layout Generators in Higher-Order Logic, Journal of Automated Reasoning, vol.17, issue.4, 2006.
DOI : 10.1007/s10817-006-9039-9

S. Pillement, Conception d'architectures reconfigurables dynamiquement : Du silicium au système, 2010.

C. Plessl and M. Platzner, Virtualization of hardware?introduction and survey, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004.

J. Pouwelse, K. Langendoen, and H. Sips, Dynamic voltage scaling on a low-power microprocessor, Proceedings of the 7th annual international conference on Mobile computing and networking , MobiCom '01, 2001.
DOI : 10.1145/381677.381701

Q. Imran-rafiq, MARTE Based Model Driven Design Methodology for Targeting Dynamically Reconfigurable FPGA Based SoCs, 2010.

A. Imran-rafiq-quadri, P. Gamatié, S. Boulet, J. Meftali, and . Dekeyser, Expressing embedded systems configurations at high abstraction levels with UML MARTE profile : Advantages, limitations and alternatives, Journal of Systems Architecture : the EUROMICRO Journal, issue.5, p.58, 2012.

J. Queille and J. Sifakis, A temporal logic to deal with fairness in transition systems, 23rd Annual Symposium on Foundations of Computer Science (sfcs 1982), pp.217-225, 1982.
DOI : 10.1109/SFCS.1982.57

P. J. Ramadge, Modular Feedback Logic for Discrete Event Systems, SIAM Journal on Control and Optimization, vol.25, issue.5, 1987.
DOI : 10.1137/0325066

P. J. Ramadge and W. M. Wonham, Supervisory control of a class of discrete event processes Analysis and Optimization of Systems, 1984.

R. Ramesham, N. Justin, . Maki, M. Ali, . Pourangi et al., Qualification of Engineering Camera for Long-Duration Deep Space Missions, 2012.

D. Ratter, FPGAs on mars, Xcell J, 2004.

P. Raymond, Lustre manual V4

E. Riccobene, P. Scandurra, A. Rosti, and S. Bocchio, A modeldriven design environment for embedded systems, DAC, pp.915-918, 2006.

L. Rioux, M. Faugère, . Marte, and . Aadl, Mise en correspondance des concepts. Génie Logiciel n ? 97, pp.4-8, 2011.

W. Royce, Managing the development of large software systems, proceedings of IEEE WESCON, 1970.

É. Rutten and P. L. Guernic, Sequencing date flow tasks in SIGNAL, Proceedings of the ACM SIGPLAN Workshop on Language, Compiler and Tool Support for Real-Time Systems, 1994.
URL : https://hal.archives-ouvertes.fr/inria-00074552

É. Rutten, É. Marchand, and F. Chaumette, An Experiment with Reactive Data-flow Tasking in Active Robot Vision, Software: Practice and Experience, vol.27, issue.5, 1997.
DOI : 10.1002/(SICI)1097-024X(199705)27:5<599::AID-SPE102>3.0.CO;2-K

URL : https://hal.archives-ouvertes.fr/hal-00908095

T. Santen and D. Seifert, Executing UML state machines, 2006.

U. Schiel and I. Mistrik, Using object-oriented analysis and design for integrated systems Systems Integration '90, Systems Integration Proceedings of the First International Conference on, pp.125-134, 1990.

D. Schmidt, Guest Editor's Introduction: Model-Driven Engineering, Computer, vol.39, issue.2, pp.25-31, 2006.
DOI : 10.1109/MC.2006.58

. Sdmetrics, Software Design Metrics tool for the UML

M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik-rabaey et al., Addressing the system-on-a-chip interconnect woes through communication-based design, Proceedings of the 38th conference on Design automation , DAC '01, pp.667-672, 2001.
DOI : 10.1145/378239.379045

. Sim2chro, Official website

E. Sotiriou-xanthopoulos, I. Koutras, G. Economakos, and D. Soudris, A reconfigurable IP characterization technique improving high-level synthesis results, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), pp.1-6, 2011.
DOI : 10.1109/DTIS.2011.5941416

B. Sreekandath and B. Priyadarshan, An integrated flow for ASIC designs with FPGA prototyping-a designer's perspective, Proceedings of WESCON'95, 1995.
DOI : 10.1109/WESCON.1995.485291

. Systemc, The Open SystemC Initiative

F. Thoma, M. Kuhnle, P. Bonnot, E. Moscu-panainte, K. Bertels et al., MORPHEUS: Heterogeneous Reconfigurable Computing, 2007 International Conference on Field Programmable Logic and Applications, pp.409-414, 2007.
DOI : 10.1109/FPL.2007.4380681

A. Mathison and T. , On Computable Numbers, with an Application to the Entscheidungsproblem . A Correction, Proceedings of the London Mathematical Society, pp.2-43544, 1938.

R. Velazco, P. Fouillat, R. Augusto, and L. Reis, Radiation Effects on Embedded Systems, 2007.
DOI : 10.1007/978-1-4020-5646-8

URL : https://hal.archives-ouvertes.fr/hal-00185087

J. Vidal, Dynamic and partial reconfigurable embedded systems design with uml, 2010.

J. Vidal, G. Florent-de-lamotte, J. Gogniat, S. Diguet, and . Guillet, Dynamic applications on reconfigurable systems: From UML model design to FPGAs implementation, 2011 Design, Automation & Test in Europe, 2011.
DOI : 10.1109/DATE.2011.5763315

URL : https://hal.archives-ouvertes.fr/hal-01167776

P. Wattebled, J. Diguet, and J. Dekeyser, Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012.
DOI : 10.1109/ReCoSoC.2012.6322884

URL : https://hal.archives-ouvertes.fr/hal-00745150

M. Wenzel, The Isabelle/Isar Reference Manual [online]. 2012

D. Whang, S. Jin, M. Charles, and . Lieber, Nanolithography Using Hierarchically Assembled Nanowire Masks, Nano Letters, vol.3, issue.7, pp.951-954, 2003.
DOI : 10.1021/nl034268a

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.1027.8713

L. Ye, J. Diguet, and G. Gogniat, Reconfigurable MPSoCs for On-Demand Computing. GRETSI, 2009.
URL : https://hal.archives-ouvertes.fr/hal-00422152

H. Yu, A MARTE based reactive model for data-parallel intensive processing : Transformation toward the synchronous model, 2008.

H. Yu, A. Gamatié, and É. Rutten, Safe design of high-performance embedded systems in an MDE framework, Innovations in Systems and Software Engineering, 2008.
DOI : 10.1007/s11334-008-0059-y

Y. Yu, Y. Lin, Z. Hu, S. Hidaka, H. Kato et al., Maintaining invariant traceability through bidirectional transformations, 2012 34th International Conference on Software Engineering (ICSE), pp.540-550, 2012.
DOI : 10.1109/ICSE.2012.6227162

URL : https://files.ifi.uzh.ch/icseweb/downloads.html

Z. Zhang and W. M. Wonham, STCT: An Efficient Algorithm for Supervisory Control Design, Symposium on Supervisory Control of Discrete Event Systems, 2001.
DOI : 10.1007/978-1-4757-6656-1_5