C. André, J. Deantoni, F. Mallet, R. , and S. , The Time Model of Logical Clocks Available in the OMG MARTE Profile, pp.201-227, 2010.
DOI : 10.1007/978-1-4419-6400-7_7

J. Deantoni and F. Mallet, TimeSquare: Treat Your Models with Logical Time, Proceedings of the 50th international conference on Objects, Models, Components, Patterns, TOOLS'12, pp.34-41, 2012.
DOI : 10.1007/978-3-642-30561-0_4

URL : https://hal.archives-ouvertes.fr/hal-00688590

D. Power and . Aceplorer, http://www.doceapower.com/products-services/ aceplorer.html, 2012.

J. Eker, J. W. Janneck, E. A. Lee, J. Liu, X. Liu et al., Taming heterogeneity - the Ptolemy approach, Proceedings of the IEEE, vol.91, issue.1, pp.127-144, 2003.
DOI : 10.1109/JPROC.2002.805829

C. Hardebolle and F. Boulanger, ModHel???X: A Component-Oriented Approach to Multi-Formalism Modeling, Models in Software Engineering, pp.247-258
DOI : 10.1007/978-3-540-69073-3_26

URL : https://hal.archives-ouvertes.fr/hal-00554780

P. Kruchten, The 4+1 View Model of architecture, IEEE Software, vol.12, issue.6, pp.42-50, 1995.
DOI : 10.1109/52.469759

J. F. Sowa and J. A. Zachman, Extending and formalizing the framework for information systems architecture, IBM Systems Journal, vol.31, issue.3, pp.590-616, 1987.
DOI : 10.1147/sj.313.0590

E. Demirli and B. Tekinerdogan, Software Language Engineering of Architectural Viewpoints, Software Architecture, pp.336-343
DOI : 10.1147/sj.263.0276

O. Mda, Object Management Group, v1, 2003.

D. Steinberg, F. Budinsky, M. Paternostro, and E. Merks, EMF: Eclipse Modeling Framework 2.0, 2009.

F. Jouault and I. Kurtev, Transforming Models with ATL, Satellite Events at the MoDELS 2005 Conference, pp.128-138, 2006.
DOI : 10.1007/11663430_14

URL : https://hal.archives-ouvertes.fr/hal-00448120

R. Hilliard, I. Malavolta, H. Muccini, and P. Pelliccione, Realizing architecture frameworks through megamodelling techniques, Proceedings of the IEEE/ACM international conference on Automated software engineering, ASE '10, pp.305-308, 2010.
DOI : 10.1145/1858996.1859057

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.464.1224

M. Clavreul, Model and Metamodel Composition: Separation of Mapping and Interpretation for Unifying Existing Model Composition Techniques, 2011.
URL : https://hal.archives-ouvertes.fr/tel-00646893

G. Kiczales, J. Lamping, A. Mendhekar, C. Maeda, C. V. Lopes et al., Aspect-oriented programming, ECOOP, pp.220-242, 1997.

A. Colyer, A. Clement, G. Harley, and M. Webster, Eclipse AspectJ: Aspect-Oriented Programming with AspectJ and the Eclipse AspectJ Development Tools, 2004.

F. Fleurey, B. Baudry, R. France, and S. Ghosh, A Generic Approach for Automatic Model Composition, Models in Software Engineering, pp.7-15, 2008.
DOI : 10.1007/978-3-540-69073-3_2

URL : https://hal.archives-ouvertes.fr/inria-00477568

M. Nassar, VUML: a viewpoint oriented UML extension, 18th IEEE International Conference on Automated Software Engineering, 2003. Proceedings., pp.373-376, 2003.
DOI : 10.1109/ASE.2003.1240341

A. Cicchetti, F. Ciccozzi, and T. Leveque, Supporting Incremental Synchronization in Hybrid Multi-view Modelling, W. on Models in Software Engineering , MoDELS Workshops, pp.89-103, 2011.
DOI : 10.1007/978-3-642-29645-1_11

F. Boulanger and C. Jacquet, Cécile Hardebolle, and Elyes Rouis. Modeling heterogeneous points of view with ModHel'X, W. on Models in Software Engineering, MoDELS Workshops, pp.310-324, 2009.

G. D. Plotkin, A structural approach to operational semantics, J. Log. Algebr. Program, pp.60-6117, 2004.

C. A. Hoare, ViewpointRetrospective, Communications of the ACM, vol.52, issue.10, pp.30-32, 2009.
DOI : 10.1145/1562764.1562779

L. Fredlund, B. Jonsson, and J. Parrow, An implementation of a translational semantics for an imperative language, In CONCUR, pp.246-262, 1990.
DOI : 10.1007/BFb0039064

A. Goderis, C. Brooks, I. Altintas, E. A. Lee, and C. Goble, Heterogeneous composition of models of computation, Future Generation Computer Systems, vol.25, issue.5, pp.552-560, 2009.
DOI : 10.1016/j.future.2008.06.014

A. Basu, M. Bozga, and J. Sifakis, Modeling Heterogeneous Real-time Components in BIP, Fourth IEEE International Conference on Software Engineering and Formal Methods (SEFM'06), pp.3-12, 2006.
DOI : 10.1109/SEFM.2006.27

URL : https://hal.archives-ouvertes.fr/hal-00375298

E. A. Lee and A. Sangiovanni-vincentelli, A framework for comparing models of computation. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.17, issue.12, pp.1217-1229, 1998.

J. Benoit-combemale, M. Deantoni, F. Vara-larsen, O. Mallet, B. Barais et al., Reifying Concurrency for Executable Metamodeling, the 6th International Conference on Software Language Engineering, 2013.
DOI : 10.1007/978-3-319-02654-1_20

P. Alexander and C. Kong, Rosetta: semantic support for model-centered systems-level design, Computer, vol.34, issue.11, pp.64-70, 2001.
DOI : 10.1109/2.963446

K. Skadron, M. R. Stan, K. Sankaranarayanan, W. Huang, S. Velusamy et al., Temperature-aware microarchitecture, ACM Transactions on Architecture and Code Optimization, vol.1, issue.1, pp.94-125, 2004.
DOI : 10.1145/980152.980157

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.135.9559

. Stan, Hotspot: a compact thermal modeling methodology for early-stage vlsi design . Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.14, issue.5, pp.501-513, 2006.

C. André, F. Mallet, and J. Deantoni, VHDL observers for clock constraint checking, International Symposium on Industrial Embedded System (SIES), 2010.
DOI : 10.1109/SIES.2010.5551372

O. Uml, Profile for Advanced and Integrated Telecommunication Services (TelcoML ) Object Management Group, 2012.

. Obeo, Uml designer, 1920.

N. Magic, Magic draw, 2013.

C. G. Cassandras and S. Lafortune, Introduction to Discrete Event Systems, 2006.

D. Helms, E. Schmidt, and W. Nebel, Leakage in CMOS Circuits ??? An Introduction
DOI : 10.1007/978-3-540-30205-6_5

W. Zhang, J. Williamson, and L. Shang, Power Dissipation, Low-Power Variation-Tolerant Design in Nanometer Silicon, pp.41-80, 2010.
DOI : 10.1007/978-1-4419-7418-1_2

D. Miltos, G. Grammatikakis, M. Kornaros, and . Coppola, Power-aware multicore SoC and NoC design, Multiprocessor System-on-Chip, pp.167-193

D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-On-Chip Design. Integrated Circuits and Systems, 2007.

F. Fallah and M. Pedram, Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits, IEICE Transactions on Electronics, vol.88, issue.4, pp.509-519, 2005.
DOI : 10.1093/ietele/e88-c.4.509

E. A. Mostafa, M. Ibrahim, H. A. Rupp, and . Fahmy, A precise highlevel power consumption model for embedded systems software, EURASIP J. Embedded Syst, pp.1-1, 2011.

L. W. Nagel, SPICE2: A Computer Program to Simulate Semiconductor Circuits, p.9602, 1975.

C. X. Huang, B. Zhang, A. Deng, and B. Swirski, The design and implementation of PowerMill, Proceedings of the 1995 international symposium on Low power design , ISLPED '95, pp.105-110, 1995.
DOI : 10.1145/224081.224100

T. Chou and K. Roy, Accurate power estimation of cmos sequential circuits. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.4, issue.3, pp.369-380, 1996.

. Chih-shun, C. Ding, M. Ying-tsui, and . Pedram, Gate-level power estimation using tagged probabilistic simulation. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol.17, issue.11, pp.1099-1107, 1998.

W. Ye, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, The design and use of simplepower, Proceedings of the 37th conference on Design automation , DAC '00, pp.340-345, 2000.
DOI : 10.1145/337292.337436

S. Gurumurthi, A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M. Kandemir et al., Using complete machine simulation for software power estimation: the SoftWatt approach, Proceedings Eighth International Symposium on High Performance Computer Architecture, p.141, 2002.
DOI : 10.1109/HPCA.2002.995705

D. Brooks, V. Tiwari, and M. Martonosi, Wattch, ACM SIGARCH Computer Architecture News, vol.28, issue.2, pp.83-94, 2000.
DOI : 10.1145/342001.339657

F. Klein, G. Araujo, R. Azevedo, R. Leao, and L. C. Santos, An efficient framework for high-level power exploration, 2007 50th Midwest Symposium on Circuits and Systems, pp.1046-1049, 2007.
DOI : 10.1109/MWSCAS.2007.4488741

V. Tiwari, S. Malik, and A. Wolfe, Power analysis of embedded software: a first step towards software power minimization. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol.2, issue.4, pp.437-445, 1994.

V. Konstantakos, A. Chatzigeorgiou, S. Nikolaidis, and T. Laopoulos, Energy consumption estimation in embedded systems, Instrumentation and Measurement Technology Conference Proceedings of the IEEE, pp.235-238, 2006.

J. Laurent, N. Julien, E. Senn, and E. Martin, Functional level power analysis: an efficient approach for modeling the power consumption of complex processors, Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp.666-667, 2004.
DOI : 10.1109/DATE.2004.1268921

URL : https://hal.archives-ouvertes.fr/hal-00013979

T. Okuhira and T. Ishihara, Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits, Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation
DOI : 10.1109/4.668984

A. Ejlali, B. M. Hashimi, and P. Eles, Low-energy standby-sparing for hard realtime systems. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, issue.3, pp.31329-342, 2012.

A. Genser, C. Bachmann, C. Steger, R. Weiss, and J. Haid, Power emulation based DVFS efficiency investigations for embedded systems, 2010 International Symposium on System on Chip, pp.173-178, 2010.
DOI : 10.1109/ISSOC.2010.5625559

. Accellera, Unified power format 1.0, 2007.

L. Cai and D. Gajski, Transaction level modeling: an overview, Proceedings of the 1st IEEEIFIP international conference on Hardware/software codesign and system synthesis, CODES+ISSS '03, pp.19-24, 2003.
DOI : 10.1109/codess.2003.1275250

O. Mbarek, A. Pegatoquet, and M. Auguin, A methodology for poweraware transaction-level models of systems-on-chip using upf standard concepts, PATMOS, pp.226-236, 2011.
URL : https://hal.archives-ouvertes.fr/hal-00662427

M. Hagner, A. Aniculaesei, and U. Goltz, UML-Based Analysis of Power Consumption for Real-Time Embedded Systems, 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications, pp.1196-1201, 2011.
DOI : 10.1109/TrustCom.2011.161

T. Arpinen, E. Salminen, T. D. Hämäläinen, and M. Hännikäinen, MARTE profile extension for modeling dynamic power management of embedded systems, Journal of Systems Architecture, vol.58, issue.5, 2011.
DOI : 10.1016/j.sysarc.2011.01.003

D. Ma and R. Bondade, Enabling power-efficient DVFS operations on silicon. Circuits and Systems Magazine, IEEE, vol.10, issue.1, pp.14-30, 2010.

A. Abdallah, A. Gamatie, and J. Dekeyser, Correct and energy-efficient design of SoCs: The H.264 encoder case study, 2010 International Symposium on System on Chip, pp.115-120, 2010.
DOI : 10.1109/ISSOC.2010.5625558

URL : https://hal.archives-ouvertes.fr/inria-00522792