.. Basse-température, 92 II.4.1. Etude de la mobilité avec et sans contrainte, II.4. Caractérisation électrique à, p.95

I. .. De-si-suspendu and .. , Fabrication d'une membrane ou nanofil, p.146

M. G. Ancona89, G. J. Ancona, and . Iafrate, Quantum correction to the equation of state of an electron gas in a semiconductor, Physical Review B, vol.39, issue.13, pp.9536-9540, 1989.
DOI : 10.1103/PhysRevB.39.9536

A. Andrieu, F. Faynot, O. Rochette, F. Barbe, J. Buj et al., TiN gate) on the Performance of <100> or <110> oriented FDSOI cMOSFETs for the 32nm Node, IEEE Symposium on, pp.50-62, 2007.

A. Kah-wee-ang-balasubramanian, N. Samudra, G. S. , and Y. Yeo, Jianqiang Lin; Chih-Hang TungStrained n-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance, Electron Devices IEEE Transactions on, vol.55857, issue.3, p.850, 2008.

A. Narain, D. Arora, R. Rios, and C. Huang, Modeling the Poly silicon Depletion Effect and Its Impact on Submicrometer, 1995.

A. Matthias-auf-der-maur, M. Povolotskyi, F. Sacconi, A. Pecchia, and A. Di-arlo, Multiscale simulation of MOS systems based on high-?? oxides, Journal of Computational Electronics, vol.49, issue.5, pp.398-402, 2008.
DOI : 10.1007/s10825-007-0160-8

. Troeger, P. Weber, K. Yashar, K. Zawadzki, and . Mistry, A 22nm High Performance and Low-Power CMOS Technology Featuring Fully-Depleted Tri- Gate Transistors , Self-Aligned Contacts and High Density MIM Capacitors IDSAT, VGS ( V ), " VLSI Symposium, pp.131-132, 2012.

. Balestra87, S. Balestra, M. Ristoloveanu, J. Benachir, T. Brini et al., Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance, IEEE Electron Device Letters, vol.8, issue.9, pp.410-412, 1987.
DOI : 10.1109/EDL.1987.26677

S. Bangsaruntip10, A. Bangsaruntip, G. M. Majumdar, S. U. Cohen, Y. Engelmann et al., Gate-all-around Silicon Nanowire

B. Bardeen, J. Brattain, and W. H. , Physical Principles Involved in Transistor Action, Physical Review, vol.75, issue.8, pp.1208-1225, 1949.
DOI : 10.1103/PhysRev.75.1208

S. Barraud, E. Sarrazin, and A. Bournel, Temperature and size dependences of electrostatics and mobility in gate-all-around MOSFET devices, Semiconductor Science and Technology, vol.26, issue.2, p.25001, 2011.
DOI : 10.1088/0268-1242/26/2/025001

B. Barraud, S. Coquand, R. Casse, M. Koyama, M. Hartmann et al., Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm, IEEE Electron Device Letters, vol.33, issue.11, p.15261528, 2012.
DOI : 10.1109/LED.2012.2212691

B. Barraud, S. Coquand, R. Maffini-alvaro, V. Samson, M. Hartmann et al., Scaling of ?-gate SOI nanowire N-and P-FET down to 10nm gate length: Size-and orientationdependent strain effects, VLSI Technology (VLSIT), 2013 Symposium on, pp.230-241, 2013.

V. S. Basker10, T. Basker, H. Standaert, C. Kawasaki, K. Yeh et al., A 0 . 063 ?m 2 in ET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch Gate, VLSI Symposium, pp.19-20, 2010.

B. Ben-akkez, I. Fenouillet-beranger, C. Cros, A. Perreau, P. Haendler et al., Impact of substrate orientation on Ultra Thin BOX Fully Depleted SOI electrical performances, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS), pp.177-183, 2012.
DOI : 10.1109/ULIS.2012.6193386

C. Andrieu, Y. Vizioz, P. Campidelli, J. M. Gautier, R. Hartmann et al., Novel integration process and performances analysis of Low STandby Power (LSTP) 3D multi-channel CMOSFET (MCFET) on SOI with metal / high-K gate stack, Symposium on VLSI Technology, pp.16-17, 2008.

B. Bernard, E. Ernst, T. Guillaumot, B. Vulliet, N. Tao-chuan-lim et al., First Internal Spacers' Introduction in Record High ION/IOFF TiN/HfO2 Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements, Electron Device Letters, vol.30, issue.2, p.148151, 2009.

B. Bidal, G. Loubet, N. Fenouillet-beranger, C. Denorme, S. Perreau et al., Folded fully depleted Bulk+ technology as a highly W-scaled planar solution, ESSDERC 2008, 38th European Solid-State Device Research Conference, pp.210-225, 2008.
DOI : 10.1109/ESSDERC.2008.4681735

URL : https://hal.archives-ouvertes.fr/hal-00392132

G. Ghibaudo and T. Skotnicki, Planar Bulk+ technology using TiN/Hf-based gate stack for low power applications, VLSI Technology Symposium on, vol.147, pp.146-163, 2008.

R. Bonam10, P. Bonam, A. Verhagen, J. Munder, and . Hartley, Performance characterization of negative resists for sub-10-nm electron beam lithography, Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol.28, issue.6, pp.34-40, 2010.
DOI : 10.1116/1.3517721

O. Bonno08, S. Bonno, D. Barraud, F. Mariolle, and . Andrieu, Effect of strain on the electron effective mobility in biaxially strained silicon inversion layers: An experimental and theoretical analysis via atomic force microscopy measurements and Kubo-Greenwood mobility calculations, Journal of Applied Physics, vol.103, issue.6, p.63715, 2008.
DOI : 10.1063/1.2896589

C. Casse, M. Thevenod, L. Guillaumot, B. Tosti, L. Martin et al., Carrier transport in HfO2/metal gate MOSFETs: physical insight into critical parameters, Electron Devices IEEE Transactions on, vol.53768, issue.4, p.759, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00145521

C. Casse, M. Barraud, S. , L. Royer, C. Koyama et al., Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires, 2012 International Electron Devices Meeting, pp.10-13, 2012.
DOI : 10.1109/IEDM.2012.6479119

D. Dellile, F. Leverd, and P. Gouraud, New Design Adapted Planar Double Gate Process for performant low standby power application, Proc. Silicon Nanoelectronics Workshop, pp.12-13, 2005.

J. B. Chang11, M. Chang, P. M. Guillorn, C. Solomon, S. U. Lin et al., Scaling of SOI in ETs down to in Width of 4 nm for the 10nm technology node, Symposium on VLSI Technology Digest of Technical Papers, pp.12-13, 2011.

C. Chee-wee, S. Maikop, and C. Yu, Mobility-enhancement technologies, Circuits and Devices Magazine, p.21, 2005.
DOI : 10.1109/MCD.2005.1438752

C. Chien-hao-chen, T. Lee, T. H. Hou, C. L. Chen, C. Chen et al., Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., pp.56-71, 2004.
DOI : 10.1109/VLSIT.2004.1345390

M. Ku, A. Khare, and . Steegen, A ost Effective 32nm High-K/ Metal Gate CMOS Technology for Low Power Applications with Single-Metal/Gate-irst Process " in VLSI Symp, Tech. Dig, pp.88-89, 2008.

J. Hen, T. Saraya, K. Miyaji, K. Shimizu, and T. Hiramoto, Experimental Study of Mobility in [110]-and [100]-Directed Multiple Silicon Nanowire GAA MOS ETs on (100) SOI, Symp. VLSI Tech. Dig, pp.32-33, 2008.

A. B. Sachid, . Hu, -. Fu, and . Yang, A 10 nm Si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25% better static noise margin, VLSI Technology (VLSIT), 2013 Symposium on, pp.218-229

C. Kim, A proposed porous methylhydrogensilsesquioxane-based low-k film with k~2.3 for intermetal dielectric application in high speed memory device, Semiconductor Manufacturing IEEE International Symposium on, vol.419, pp.417-430, 2005.

C. Cho, H. Seo, K. Jeong, W. C. Kim, Y. Lim et al., Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications, 2011 International Electron Devices Meeting, pp.5-7, 2011.
DOI : 10.1109/IEDM.2011.6131556

Y. Choi01, N. Choi, P. Lindert, S. Xuan, D. Tang et al., Sub-20nm MOS in ET Technologies, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.421-424, 2001.

C. Choi, . Sookyung, M. J. Word, V. Kumar, and I. Adesida, Comparative study of thermally cured and electron-beam-exposed hydrogen silsesquioxane resists, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol.26, issue.5, p.16541659, 2008.
DOI : 10.1116/1.2960565

C. Choi, K. Asano, N. Lindert, V. Subramanian, . Tsu-jae et al., Ultra-thin body SOI MOSFET for deep-sub-tenth micron era, Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International, pp.919-924, 1999.

C. Colinge, J. Quinn, A. J. Floyd, L. Redmond, G. Alderman et al., Lowtemperature electron mobility in Trigate SOI MOSFETs, Electron Device Letters, vol.27122, issue.2, p.120, 2006.

C. Constancias, C. Dalzotto, B. Michallon, P. Wallace, J. Saib et al., Fabrication of large area ultrathin silicon membrane: Application for high efficiency extreme ultraviolet diffraction gratings, Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, vol.28, issue.1, pp.194-197, 2010.
DOI : 10.1116/1.3290746

URL : https://hal.archives-ouvertes.fr/hal-00454443

D. Cooper, J. Rouviere, A. Béché, S. Kadkhodazadeh, E. S. Semenova et al., Quantitative strain mapping of InAs/InP quantum dots with 1???nm spatial resolution using dark field electron holography, Applied Physics Letters, vol.99, issue.26, pp.261911-261911, 2011.
DOI : 10.1063/1.3672194

C. R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz et al., Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width, 13th International Conference on Ultimate Integration on Silicon (ULIS), 2012, pp.37-43, 2012.

C. R. Coquand, M. Cassé, S. Barraud, P. Leroux, D. Cooper et al., Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width, 2012 Symposium on VLSI Technology (VLSIT), pp.13-25, 2012.
DOI : 10.1109/VLSIT.2012.6242437

C. R. Coquand, S. Monfray, J. Pradelles, L. Martin, M. Samson et al., On the Optimization of Ebeam Lithography Using Hydrogen Silsesquioxane (HSQ) for Innovative Self-Aligned CMOS Process, ECS Transactions, vol.53, issue.3, pp.177-184, 2013.
DOI : 10.1149/05303.0177ecst

URL : https://hal.archives-ouvertes.fr/hal-01020074

C. R. Coquand, S. Monfray, S. Barraud, M. Samson, C. Arvet et al., Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors, Symposium on VLSI Technology (VLSI), pp.2013226-2013237, 2013.

C. R. Coquand, S. Barraud, M. Cassé, M. Koyama, V. Maffini-alvaro et al., De Salvo, Low-Temperature Transport Characteristics in SOI and sSOI Nanowires Down to 8nm Width: Evidence of IDS and Mobility Oscillations, Proceedings of the European Solid-State Device Research Conference (ESSDERC), p.2013

C. R. Coquand, M. Jaud, O. Rozeau, A. Idrissi-eloudrhiri, S. Martinie et al., Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp.3-2013
DOI : 10.1109/S3S.2013.6716523

C. R. Coquand, M. Cassé, S. Barraud, D. Cooper, V. Maffini-alvaro et al., Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width, IEEE Transactions on Electron Devices, vol.60, issue.2, p.727732, 2013.
DOI : 10.1109/TED.2012.2231684

URL : https://hal.archives-ouvertes.fr/hal-01017518

C. R. Coquand, S. Barraud, M. Cassé, P. Leroux, C. Vizioz et al., Scaling of high-??/metal-gate TriGate SOI nanowire transistors down to 10nm width, Solid-State Electronics, vol.88, pp.32-36, 2013.
DOI : 10.1016/j.sse.2013.04.006

URL : https://hal.archives-ouvertes.fr/hal-01002171

D. Dennard, R. H. Gaensslen, F. H. Kuhn, L. Yu, and H. N. , Design of micron MOS switching devices, Electron Devices Meeting International, vol.18170, p.168, 1972.

D. Dennard, R. H. Gaensslen, F. H. Rideout, V. L. Bassous, E. Leblanc et al., Design of ion-implanted MOSFET's with very small physical dimensions Solid- State Circuits, IEEE Journal, vol.9268, issue.5, p.256, 1974.

V. Destefanis09, D. Destefanis, J. M. Rouchon, A. M. Hartmann, L. Papon et al., Structural properties of tensily strained Si layers grown on SiGe (100), (110), and (111) virtual substrates Structural properties of tensily strained Si layers grown on SiGe " 100 ?, Journal of Applied Physics, vol.043508, issue.106, 2009.

V. Destefanis10, J. Destefanis, J. Hartmann, V. Huguenin, M. Delaye et al., abrication , structural and electrical properties of ( 1 1 0 ) localized silicon-on-insulator devices, Semiconducteur science and technology, 2010.

D. Dornel, E. Ernst, T. Barbe, J. Hartmann, J. M. Delaye et al., Hydrogen annealing of arrays of planar and vertically stacked Si nanowires, Applied Physics Letters, vol.91, issue.23, pp.233502233502-3, 2007.
DOI : 10.1063/1.2818678

B. S. Doyle03, S. Doyle, M. Datta, S. Doczy, B. Hareland et al., High performance fully-depleted tri-gate CMOS transistors, IEEE Electron Device Letters, vol.24, issue.4, pp.263-265, 2003.
DOI : 10.1109/LED.2003.810888

Y. Ekinci07, H. H. Ekinci, C. Solak, J. Padeste, M. P. Gobrecht et al., 20nm Line/space patterns in HSQ fabricated by EUV interference lithography, Microelectronic Engineering, vol.84, issue.5-8, pp.5-8, 2007.
DOI : 10.1016/j.mee.2007.01.213

O. Brevard and . Weber, Hybrid DSOI / Bulk high-k / Metal gate platform for Low Power ( LP ) multimedia technology, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.28-34, 2009.

Y. Pernet, L. Campidelli, P. Pinzelli, M. Gouraud, C. Cassé et al., Efficient Multi-V T FDSOI technology with UTBOX for low power circuit design, VLSI Symposium, pp.65-66, 2010.

J. Fruleux-cornu06-frederique-fruleux-cornu, E. Penaud, M. Dubois, and . Rancois, Optimisation of HSQ e-beam lithography for the patterning of FinFET transistors, Microelectronic Engineering, vol.83, issue.4-9, pp.776-779, 2006.
DOI : 10.1016/j.mee.2006.01.159

Y. M. Georgiev05, W. Georgiev, A. Henschel, and H. Kurz, Surface roughness of hydrogen silsesquioxane as a negative tone electron beam resist, Vacuum, vol.77, issue.2, pp.117-123, 2005.
DOI : 10.1016/j.vacuum.2004.07.080

G. Ghani, T. Armstrong, M. Auth, C. Bost, M. Charvat et al., A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors, IEEE International Electron Devices Meeting 2003, pp.8-10
DOI : 10.1109/IEDM.2003.1269442

G. Ghibaudo09, M. Ghibaudo, K. Mouis, I. Bennamane, A. Pappas et al., Electrical transport characterization of nano CMOS devices with ultra-thin silicon film, 2009 International Workshop on Junction Technology, pp.58-63, 2009.
DOI : 10.1109/IWJT.2009.5166220

A. E. Grigorescu07, M. Grigorescu, .. W. Van-der-krogt, P. Hagen, and . Kruit, 10nm lines and spaces written in HSQ, using electron beam lithography, Microelectronic Engineering, vol.84, issue.5-8, pp.5-8, 2007.
DOI : 10.1016/j.mee.2007.01.022

S. Habicht10, S. Habicht, Q. T. Este, S. Zhao, and . Mantl, Hole mobilities and electrical characteristics of ? -gated silicon nanowire array FETs with 110 -and 100 channel orientation, IEEE Transactions on Electron Devices, pp.372-375, 2010.

J. M. Hartmann13, V. Hartmann, J. P. Benevent, M. Barnes, D. Veillerot et al., Mushroom-free selective epitaxial growth of Si, SiGe and SiGe:B raised sources and drains, Solid-State Electronics, vol.83, pp.10-17, 2013.
DOI : 10.1016/j.sse.2013.01.033

. Hoyt, abrication and characterization of suspended uniaxial ten-sile strained-Si nanowires for gate-all-around n-MOS ETs, E S Trans, vol.16, issue.10, pp.57-68, 2008.

P. Hashemi09, S. Hashemi, L. Member, J. L. Gomez, and . Hoyt, Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter, IEEE Electron Device Letters, vol.30, issue.4, pp.401-403, 2009.
DOI : 10.1109/LED.2009.2013877

H. Hashemi, P. Kobayashi, M. Majumdar, A. Yang, L. A. Baraskar et al., Highperformance Si1?xGex channel on insulator trigate P ETs featuring an implantfree process and aggressively-scaled fin and gate dimensions, VLSI Technology (VLSIT), 2013 Symposium on, pp.18-29, 2013.

H. Hisamoto, D. Wen-chin-lee, J. Kedzierski, E. Anderson, H. Takeuchi et al., A folded-channel MOSFET for deepsub-tenth micron era, Electron Devices Meeting, 1998. IEDM '98. Technical Digest., International, pp.1032-1038, 1998.

H. Horiguchi, N. Usuki, T. Goto, K. Futatsugi, T. Sugii et al., A Direct Tunneling Memory (DTM) utilizing novel floating gate structure, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318), pp.922-927, 1999.
DOI : 10.1109/IEDM.1999.824299

. Hu12 and . Hu, Thin-body FinFET as scalable low voltage transistor, Proceedings of Technical Program of 2012 VLSI Technology, System and Application, pp.1-4, 2012.

H. Huang, W. Lee, C. Kuo, D. Hisamoto, L. Chang et al., Sub 50-nm FinFET: PMOS, Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International, pp.67-72, 1999.

H. Hubert, A. Nowak, E. Tachi, K. Maffini-alvaro, V. Vizioz et al., A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with Gate-All-Around or independent gates (&#x03C6;-Flash), suitable for full 3D integration, 2009 IEEE International Electron Devices Meeting (IEDM), 2009.
DOI : 10.1109/IEDM.2009.5424260

J. L. Huguenin10, G. Huguenin, S. Bidal, D. Denorme, N. Fleury et al., Gate-all-around technology: Taking advantage of ballistic transport?, Solid-State Electronics, vol.54, issue.9, pp.883-889, 2010.
DOI : 10.1016/j.sse.2010.04.029

K. Samson, N. Benotmane, Y. Loubet, F. Campidelli, F. Leverd et al., Localized SOI logic and bulk I/O devices co-integration for Low power System-on-hip technology, pp.118-119, 2010.

H. Huguenin, J. Lacord, J. Monfray, S. Coquand, R. Skotnicki et al., Comparative study of circuit perspectives for multi-gate structures at sub-10nm node, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp.107-119, 2011.
DOI : 10.1109/ESSDERC.2011.6044223

I. Inaba, S. Okano, K. Izumida, T. Kaneko, A. Kawasaki et al., FinFET: the prospective multi-gate device for future SoC applications, Solid-State Device Research Conference, p.4952, 2006.

T. Irisawa06, T. Irisawa, T. Numata, N. Tezuka, S. Sugiyama et al., Electron Transport Properties of Ultrathin-body and Tri-gate SOI nMOSFETs with Biaxial and Uniaxial Strain, 2006 International Electron Devices Meeting, 2006.
DOI : 10.1109/IEDM.2006.346811

B. Toffoli, S. Giffard, and . Deleonibus, ? ETs transistors with TiN metal gate and HfO 2 down to 10nm, VLSI Symposium, pp.112-113, 2005.

J. Jan, C. Bai, P. Biswas, S. Buehler, M. Chen et al., A 45nm low power system-on-chip technology with dual gate (logic and I/O) high-k/metal gate strained silicon transistors, 2008 IEEE International Electron Devices Meeting, pp.15-17, 2008.
DOI : 10.1109/IEDM.2008.4796772

J. Jan, C. Agostinelli, M. Buehler, M. Chen, Z. Choi et al., A 32nm SoC platform technology with 2nd generation high-k/metal gate transistors optimized for ultra low power, high performance, and high density product applications, Electron Devices Meeting (IEDM), 2009.

A. Rahman, J. Rizk, W. Shin, K. Soumyanath, H. Tashiro et al., RF CMOS technology scaling in Highk/metal gate era for RF SoC (system-on-chip) applications, Electron Devices Meeting (IEDM) IEEE International, pp.6-8, 2010.

M. Jurczak00 and . Jurczak, Silicon-on-Nothing (SON)-an innovative process for advanced CMOS, IEEE Transactions on Electron Devices, vol.47, issue.11, p.2179, 2000.
DOI : 10.1109/16.877181

J. M. Jurczak, T. Skotnicki, M. B. Paoli, J. Tormen, C. Regolini et al., SON (Silicon On Nothing) -A NEW, VLSI Symposium, pp.29-30, 1999.

K. Kavalieros, J. Doyle, B. Datta, S. Dewey, G. Doczy et al., Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., pp.50-50, 2006.
DOI : 10.1109/VLSIT.2006.1705211

H. Kawasaki07 and . Kawasaki, in ET Process and Integration Technology for High Performance LSI in 22, international workshop on junctions, pp.3-8, 2007.

K. Kumar, J. Maitra, . Wang, . Yeh, M. Wang et al., hallenges and Solutions of FinFET Integration in an SRAM Cell and a Logic Circuit for 22 nm node and beyond, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.289-292, 2009.

K. Khakifirooz, A. , K. Cheng, B. Jagannathan, P. Kulkarni et al., Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond, 2010 IEEE International Solid-State Circuits Conference, (ISSCC), pp.152-159, 2010.
DOI : 10.1109/ISSCC.2010.5434014

K. Koyama, M. Casse, M. Coquand, R. Barraud, S. Iwai et al., Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp.73-90, 2012.
DOI : 10.1109/ESSDERC.2012.6343336

M. Koyama13, M. Koyama, R. Cassé, S. Coquand, C. Barraud et al., Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs, Solid-State Electronics, vol.84, pp.46-52, 2013.
DOI : 10.1016/j.sse.2013.02.024

K. J. Kuhn12a, U. Kuhn, A. Avci, M. D. Cappellani, M. Giles et al., The ultimate MOS device and beyond, 2012 International Electron Devices Meeting, pp.8-9, 2012.

K. J. Kuhn12b and . Kuhn, onsiderations for Ultimate MOS Scaling, IEEE Transactions on Electron Devices, vol.59, issue.7, pp.1813-1828, 2012.

J. Lacord12a, J. Lacord, S. Huguenin, R. Monfray, T. Coquand et al., Comparative study of circuit perspectives for multi-gate structures at sub-10nm node, Solid-State Electronics, vol.74, pp.25-31, 2012.
DOI : 10.1016/j.sse.2012.04.007

L. Lacord, J. Ghibaudo, . Gerard, and F. Boeuf, Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures, IEEE Transactions on Electron Devices, vol.59, issue.5, p.13321344, 2012.
DOI : 10.1109/TED.2012.2187454

H. Lee09, J. Lee, S. Wi, H. Nam, K. Kim et al., Two-step resistdevelopment process of hydrogen silsesquioxane for high-density electron-beam nanopatterning, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol.27, issue.1, p.188, 2009.

L. Lee, B. H. Kang, L. J. Qiw, R. Nieh, Y. Jeon et al., Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application, IEEE Int. Electron DeviceMeeting Tech. Digest, p.556, 1999.

K. Lepinay13, F. Lepinay, R. Lorut, T. Pantel, and . Epicier, Chemical 3D tomography of 28nm high K metal gate transistor: STEM XEDS experimental method and results, Micron, vol.47, pp.43-49, 2013.
DOI : 10.1016/j.micron.2013.01.004

L. Lim, J. Thompson, S. E. Fossum, and J. G. , Comparison of Threshold-Voltage Shifts for Uniaxial and Biaxial Tensile-Stressed n-MOSFETs, IEEE Electron Device Letters, vol.25, issue.11, p.731733, 2004.
DOI : 10.1109/LED.2004.837581

C. Lin10, J. Lin, M. Chang, A. Guillorn, P. Bryant et al., Nonplanar device architecture for 15nm node: in ET or trigate?, 2010 IEEE International SOI Conference (SOI), pp.1-2, 2010.

T. Liow07, K. Liow, R. T. Tan, C. Lee, G. S. Tung et al., With Silicon ? Carbon Source and Drain Stressors and Tensile Capping Layer, pp.1014-1017, 2007.

T. Liow08, S. Liow, K. Member, D. Tan, R. Weeks et al., Strained n-Channel FinFETs Featuring In Situ Doped Silicon ? arbon ( Si 1 ? y y ) Source and Drain Stressors With High arbon ontent, IEEE TRANSACTIONS ON ELECTRON DEVICES, vol.55, issue.9, pp.2475-2483, 2008.

L. Liu, P. Chang, T. Yang, Y. Cheng-;-sze, and S. M. , Effects of NH3-plasma nitridation on the electrical characterizations of low-k hydrogen silsesquioxane with copper interconnects, Electron Devices IEEE Transactions on, vol.47, issue.9, p.17331739, 2000.

W. Liu02, C. Liu, W. Yang, B. Chen, M. Dai et al., The structural transformation and properties of spin-on poly(silsesquioxane) films by thermal curing, Journal of Non-Crystalline Solids, vol.311, issue.3, pp.233-240, 2002.

G. Khare, B. Shahidi, R. Doris, and . Sampson, Impact of Back Bias on Ultra-Thin Body and BOX (UTBB) Devices, VLSI Symposium, pp.160-161, 2011.

P. T. Liu98, C. Y. Liu, S. M. Chang, F. Sze, Y. Pan et al., The effects of plasma treatment for low dielectric constant hydrogen silsesquioxane ( HSQ ), Thin Solid ilms, vol.332, pp.345-350, 1998.

F. Lorut08, D. Lorut, and . Delile, Advanced FIB-based sample preparation for 3D characterization of 45nm ICs, Microscopy and Microanalysis, vol.14, issue.S2, pp.1002-1003, 2008.
DOI : 10.1017/S1431927608084572

L. Loubet, T. Kormann, G. Chabanne, and S. Denorme, Didier Dutartre, Selective etching of Si1-xGex versus Si with gaseous HCl for the formation of advanced CMOS devices, Thin Solid Films, vol.517, issue.1 3

L. Lujan, G. S. Kubicek, S. De-gendt, S. Heyns, M. Magnus et al., Mobility degradation in high-k transistors: the role of the charge scattering European Solid-State Device Research, ESSDERC '03. 33rd Conference on, pp.399-415, 2003.

M. Maleville and C. , Extending planar device roadmap beyond node 20nm through ultra thin body technology, Proceedings of 2011 International Symposium on VLSI Technology, Systems and Applications, pp.25-27, 2011.
DOI : 10.1109/VTSA.2011.5872261

V. R. Manfrinato11, L. L. Manfrinato, H. G. Cheong, D. Duan, H. I. Winston et al., Sub-5keV electron-beam lithography in hydrogen silsesquioxane resist, Microelectronic Engineering, vol.88, issue.10, pp.3070-3074, 2011.
DOI : 10.1016/j.mee.2011.05.024

L. Martin09, S. Martin, B. Manakli, J. Icard, R. Pradelles et al., Development of multiple pass exposure in electron beam direct write lithography for sub-32nm nodes, Photomask Technology 2009, 2009.
DOI : 10.1117/12.829893

L. Martin10, S. Martin, B. Manakli, J. Icard, R. Pradelles et al., Multiple pass exposure in e-beam lithography: application to the sub-22nm nodes, Alternative Lithographic Technologies II, 2010.
DOI : 10.1117/12.846907

M. Mazurier, J. Weber, O. Andrieu, F. Toffoli, A. Rozeau et al., On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells, IEEE Transactions on Electron Devices, vol.58, issue.8, p.23262336, 2011.
DOI : 10.1109/TED.2011.2157162

M. Zhao-min, . Hen-baoqin, L. Xie-hangqing, N. Ming, and . Jiebing, Study of process of HSQ in electron beam lithography, 2010 IEEE 5th International Conference on Nano/Micro Engineered and Molecular Systems, pp.1021-1024, 2010.
DOI : 10.1109/NEMS.2010.5592584

S. Monfray04 and . Monfray, SON (silicon-on-nothing) technological CMOS platform: highly performant devices and SRAM cells, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004., pp.635-638, 2004.
DOI : 10.1109/IEDM.2004.1419246

S. Monfray07 and . Monfray, Localized SOI technology: an innovative Low Cost self-aligned process for Ultra Thin Si-film on thin BOX integration for Low Power applications, 2007 IEEE International Electron Devices Meeting, pp.693-696, 2007.
DOI : 10.1109/IEDM.2007.4419040

S. Monfray08, F. Monfray, P. Boeuf, G. Coronel, S. Bidal et al., Silicon-On-Nothing (SON) applications for Low Power technologies, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, pp.8-11, 2008.
DOI : 10.1109/ICICDT.2008.4567232

S. Monfray10, J. Monfray, M. Huguenin, M. Martin, C. Samson et al., A solution for an ideal Planar Multi-Gates Process for ultimate MOS ?, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.257-260, 2010.

N. Na, M. Nowak, E. J. Haensch, W. Cai, and J. , The effective drive current in CMOS inverters, Digest. International Electron Devices Meeting,, pp.121-129, 2002.
DOI : 10.1109/IEDM.2002.1175793

A. Nainani12, S. Nainani, V. Gupta, M. Moroz, Y. Choi et al., Is strain engineering scalable in in ET era ? : teaching the old dog some new tricks, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.427-430, 2012.

H. Namatsu98, Y. Namatsu, K. Takahashi, T. Yamazaki, M. Yamaguchi et al., Three-dimensional siloxane resist for the formation of nanopatterns with minimum linewidth fluctuations, Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol.16, issue.1, pp.69-76, 1998.
DOI : 10.1116/1.589837

S. Linder, N. Lucarini, P. Lustig, K. Mclaughlin, V. Onishi et al., 22nm High- Performance SOI Technology Featuring Dual-Embedded Stressors , Epi-Plate High-K Deep-Trench Embedded DRAM and Self-Aligned Via 15LM BEOL, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.52-55, 2012.

N. Niquet, C. Delerue, and C. Krzeminski, Effects of Strain on the Carrier Mobility in Silicon Nanowires, Nano Letters, vol.12, issue.7, pp.3545-3550, 2012.
DOI : 10.1021/nl3010995

URL : https://hal.archives-ouvertes.fr/hal-00787472

T. Ohtou08, T. Ohtou, T. Saraya, and . Hiramoto, Variable-Body-Factor SOI MOSFET With Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control, IEEE Transactions on Electron Devices, vol.55, issue.1, pp.40-47, 2008.
DOI : 10.1109/TED.2007.912612

D. L. Olynick10, . Olynick, B. Ord, A. Schipotinin, D. Ogletree et al., electron-beam-induced desorption, High performance Hi-K + metal gate strain enhanced transistors on (110) silicon," Electron Devices Meeting, pp.581-587, 2008.
DOI : 10.1116/1.3425632

S. Luo and . Natarajan, High performance 32 nm logic technology featuring 2nd generation high-k +metal gate transistors, IEDM Tech. Dig, pp.659-662, 2009.

P. Gary-patton-pham08, A. Pham, and B. Meinerzhagen, Evolution and Expansion of SOI in VLSI Technologies: Planar to 3D A fast k.p solver for hole inversion layers with an efficient 2D k-space discretization, IEEE International SOI Conference J. omput. Electon, vol.7, pp.99-102, 2008.

N. Pons13, F. Pons, M. Triozon, R. Jaud, S. Coquand et al., Density Gradient calibration for 2D quantum confinement: Tri-Gate SOI transistor application, 2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp.184-187, 2013.
DOI : 10.1109/SISPAD.2013.6650605

P. Pouydebasque, A. Denorme, S. Loubet, N. Wacquez, R. ;. Bustos et al., High-Performance High-K /Metal Planar Self-Aligned Gate-All-Around CMOS Devices, Nanotechnology IEEE Transactions on, vol.7557, issue.5, p.551, 2008.

R. J. Robertson, E. Raissi, J. P. Maria, and A. I. Kingon, Band Alignments of High-K Dielectrics on Si and Pt, Proc.Mater. Res. Soc. Symp, p.87, 1999.
DOI : 10.1063/1.110761

R. F. Rochette, M. Cassé, M. Mouis, A. Haziot, T. Pioger et al., Piezoresistance effect of strained and unstrained fully-depleted silicon-on-insulator MOSFETs integrating a HfO2/TiN gate stack, Solid-State Electronics, vol.53, issue.3, pp.392-396, 2009.
DOI : 10.1016/j.sse.2009.01.017

S. Sacconi, F. Jancu, . Jean-marc, . Povolotskyi, D. Michael et al., Full-Band Tunneling in High-? Oxide MOS Structures, Electron Devices IEEE Transactions on, vol.54, issue.12, p.31683176, 2007.

S. Sachid, A. B. , and C. Hu, A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes, 2012 IEEE International SOI Conference (SOI), pp.1-4, 2012.
DOI : 10.1109/SOI.2012.6404367

M. Saitoh08, A. Saitoh, K. Kaneko, T. Okano, S. Kinoshita et al., Three-Dimensional Stress Engineering in FinFETs for Mobility / Onurrent Enhancement and Gate urrent Reduction, VLSI Symposium, pp.18-19, 2008.

S. Saitoh, M. Nakabayashi, Y. Ota, K. Uchida, K. Numata et al., Understanding of short-channel mobility in tri-gate nanowire MOSFETs and enhanced stress memorization technique for performance improvement, 2010 International Electron Devices Meeting, pp.6-8, 2010.
DOI : 10.1109/IEDM.2010.5703475

S. Saitoh, M. Nakabayashi, Y. Ota, K. Uchida, K. Numata et al., Performance Improvement by Stress Memorization Technique in Trigate Silicon Nanowire MOSFETs, IEEE Electron Device Letters, vol.33, issue.1, p.8, 2012.
DOI : 10.1109/LED.2011.2171315

S. Saitoh, M. Ota, K. Tanaka, C. Uchida, K. Numata et al., 10nm-diameter tri-gate silicon nanowire MOSFETs with enhanced high-field transport and Vth tunability through thin BOX, VLSI Technology (VLSIT), 2012 Symposium on, pp.12-14, 2012.
DOI : 10.1109/vlsit.2012.6242436

S. Sasaki, Y. Okashita, K. Nakamoto, K. Kitaoka, T. Mizuno et al., Conformal doping for FinFETs and precise controllable shallow doping for planar FET manufacturing by a novel B2H6/Helium Self-Regulatory Plasma Doping process, Electron Devices Meeting, pp.15-17, 2008.

S. Signamarcheix, T. Andrieu, F. Biasse, B. Cassé, M. Papon et al., Fully depleted silicon on insulator MOSFETs on (110) surface for hybrid orientation technologies, EuroSOI Conference, 2010.
DOI : 10.1016/j.sse.2011.01.013

S. Sunil, K. Singh, A. A. Kumbhar, and R. O. Dusane, Resisting oxygen plasma damage in low-k hydrogen silsesquioxane films by hydrogen plasma treatment, Materials Letters, vol.60, pp.13-14, 2006.

S. Skotnicki and T. , Competitive SOC with UTBB SOI, IEEE 2011 International SOI Conference, pp.3-6, 2011.
DOI : 10.1109/SOI.2011.6081792

S. Sung-dae, M. Suk, Y. Li, . Yeoh, K. H. Kyoung-hwan-yeo et al., Investigation of nanowire size dependency on TSNWFET, Electron Devices Meeting IEEE International, vol.894, pp.891-901, 2007.

Y. Sun07, S. E. Sun, T. Thompson, and . Nishida, Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors field-effect transistors, 2007.

T. Tachi, K. Casse, M. Jang, D. Dupr, A. Hubert et al., Relationship between mobility and high-k interface properties in advanced Si and SiGe nanowires, 2009 IEEE International Electron Devices Meeting (IEDM), 2009.
DOI : 10.1109/IEDM.2009.5424360

URL : https://hal.archives-ouvertes.fr/hal-00603809

K. Tachi10, M. Tachi, S. Cassé, C. Barraud, A. Dupré et al., Experimental study on carrier transport limiting phenomena in 10 nm width nanowire MOS transistors, International Electron Devices Meeting Technical Digest, pp.784-787, 2010.

T. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, On the Universality of Inversion Layer Mobility in Si MOS ET's: Part II-Effects of Surface Orientation, IEEE Trans. Electron Devices, pp.41-2363, 1994.

T. S. Takagi, J. Hoyt, J. Welser, and J. Gibbons, Comparative study of phonon???limited mobility of two???dimensional electrons in strained and unstrained Si metal???oxide???semiconductor field???effect transistors, Journal of Applied Physics, vol.80, issue.3, pp.1567-1577, 1996.
DOI : 10.1063/1.362953

M. Togo12, J. W. Togo, L. Lee, T. Pantisano, R. Chiarella et al., Phosphorus Doped Si Source Drain and SiGe hannel for Scaled Bulk in ETs, 2012 International Electron Devices Meeting, pp.423-426, 2012.

K. Uchida05, T. Uchida, K. Krishnamohan, Y. Saraswat, and . Nishi, Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., pp.129-132, 2005.
DOI : 10.1109/IEDM.2005.1609286

K. Uchida08, M. Uchida, T. Saitoh, and . Orporation, Stress Engineering in (100) and (110) nMOS ETs, pp.12-15, 2008.

U. Uchida, K. Saitoh, and M. , Carrier transport and stress engineering in advanced nanoscale MOS transistors, 2009 International Symposium on VLSI Technology, Systems, and Applications, pp.27-29, 2009.
DOI : 10.1109/VTSA.2009.5159267

K. Uchida06, A. Uchida, M. Kinoshita, and . Saitoh, Carrier Transport in (110) nMOSFETs: Subband Structures, Non-Parabolicity, Mobility Characteristics, and Uniaxial Stress Engineering, 2006 International Electron Devices Meeting, pp.11-13, 2006.
DOI : 10.1109/IEDM.2006.346943

T. Conard, R. Vos, R. Rooyackers, S. Van-elshocht, N. Collaert et al., Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs, VLSI Technology Symposium on, vol.15, pp.14-17, 2008.

A. Veloso11, G. Veloso, T. Eneman, M. Kauerauf, S. Dehan et al., Gate-First Technology for aggressively scaled EOT Logic, MOS, " VLSI Symposium, pp.34-35, 2011.

B. Guillaumot, Y. Le-tiec, P. Besson, B. Biasse, F. Allain et al., Bonded planar doublemetal-gate NMOS transistors down to 10 nm, Electron Device Letters, vol.26, issue.5, p.317319, 2005.

M. Vinet12, A. Vinet, L. Kumar, S. Grenouillet, N. Ponoth et al., Enabling the use of ion implantation for ultra-thin FDSOI n-MOS ETs, 2012.

M. P. Judong, N. Samson, B. Vuillet, T. Guillaumot, P. Ernst et al., A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels : A High Co-Integration Potential, pp.534-535, 2006.
URL : https://hal.archives-ouvertes.fr/hal-00525089

O. Weber07, T. Weber, T. Irisawa, M. Numata, N. Harada et al., Examination of Additive Mobility Enhancements for Uniaxial Stress Combined with Biaxially Strained Si, Biaxially Strained SiGe and Ge hannel MOS ETs, International Electron Devices Meeting, pp.719-722, 2007.

W. Weber, O. Faynot, O. Andrieu, F. Buj-dufournet, C. Allain et al., High immunity to threshold voltage variability in undoped ultrathin FDSOI MOSFETs and its physical understanding, Electron Devices Meeting, pp.15-17, 2008.

. Perreau, Work-function Engineering in Gate First Technology for Multi-V T Dual-Gate DSOI MOS on UTBOX, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.3-4, 2010.

J. Widiez04, F. Widiez, M. Daugé, T. Vinet, B. Poiroux et al., Experimental Gate Misalignment Analysis on Double Gate, IEEE lntemational SO1 Conference, pp.185-186, 2004.

J. Widiez05, J. Widiez, M. Lolivier, T. Vinet, B. Poiroux et al., Experimental Evaluation of Gate Architecture Influence on DG SOI MOSFETs Performance, IEEE Transactions on Electron Devices, vol.52, issue.8, pp.1772-1779, 2005.
DOI : 10.1109/TED.2005.851824

Y. T. Yamashita, V. S. Basker, T. Standaert, C. Yeh, T. Yamamoto et al., Sub-25nm FinFET with Advanced Fin Formation and Short Channel Effect Engineering, VLSI Symposium, pp.14-15, 2011.

Y. M. Yan, J. Lee, B. Ofuonye, S. Hoi, J. H. Jang et al., Effects of saltydeveloper temperature on electron-beam-exposed hydrogen silsesquioxane resist for ultradense pattern transfer, J. Vacuum. Sci. Technol, vol.28, issue.6, pp.23-27, 2010.

C. Yang02, W. Yang, and . Hen, The structures and properties of hydrogen silsesquioxane (HSQ) films produced by thermal curing, Journal of Materials Chemistry, vol.12, issue.4, pp.1138-1141, 2002.
DOI : 10.1039/b107697n

Y. Yang, E. P. Gusev, M. Ieong, O. Gluschenkov, D. C. Boyd et al., Performance dependence of CMOS on silicon substrate orientation for ultrathin oxynitride and HfO2 gate dielectrics, Electron Device Letters, vol.24341, issue.5, p.339, 2003.

Y. Yang, J. F. Xia, Z. L. Du, G. Liu, X. Y. Han et al., Coulomb Scattering induced mobility degradation in Ultrathin-body SOI MOSFETs with high-k gate stack Solid-State and Integrated Circuit Technology, ICSICT '06. 8th International Conference on, pp.1315-1338, 2006.

J. K. Yang06b, V. Yang, K. K. Anant, and . Berggren, Enhancing etch resistance of hydrogen silsesquioxane via postdevelop electron curing *, J. Vacuum. Sci. Technol. Sci. Technol, vol.24, issue.6, pp.3157-3161, 2006.

Y. Yang, . Chan, W. C. Victor, K. K. Chan, L. Shi et al., Hybrid-orientation technology (HOT): opportunities and challenges, Electron Devices IEEE Transactions on, vol.53978, issue.5, p.965, 2006.

S. Maciejewski, J. Luning, E. Pellerin, and . Leobandung, High-performance nMOSFET with in-situ Phosphorus-doped embedded Si:C (ISPD eSi:C) sourcedrain stressor, IEDM Technical Digest. IEEE International Electron Devices Meeting, pp.1-4, 2008.

Y. K. , S. Yi, K. Trivedi, H. C. Floresca, H. Yuk et al., Room-Temperature Quantum Confinement Effects in Transport Properties of Ultrathin Si Nanowire Field-Effect Transistors, Nano Lett, issue.12, pp.11-5465, 2011.

H. Yoshioka, N. M. Suda, and T. Kimoto, Mobility oscillation by one-dimensional quantum confinement in Si-nanowire metal-oxide-semiconductor field effect transistors, Journal of Applied Physics, vol.106, issue.3, p.34312, 2009.
DOI : 10.1063/1.3187803

V. Samson, C. Maffini-alvaro, S. Tabone, D. Barnola, G. Munteanu et al., Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width, 13th International Conference on Ultimate Integration on Silicon (ULIS), pp.37-43, 2012.

R. Coquand, M. Cassé, S. Barraud, P. Leroux, D. Cooper et al., Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width, 2012 Symposium on VLSI Technology (VLSIT), pp.13-25, 2012.
DOI : 10.1109/VLSIT.2012.6242437

R. Coquand, S. Monfray, J. Pradelles, L. Martin, M. Samson et al., On the Optimization of Ebeam Lithography Using Hydrogen Silsesquioxane (HSQ) for Innovative Self-Aligned CMOS Process, ECS Transactions, vol.53, issue.3, pp.177-184, 2013.
DOI : 10.1149/05303.0177ecst

URL : https://hal.archives-ouvertes.fr/hal-01020074

R. Coquand, S. Monfray, S. Barraud, M. Samson, C. Arvet et al., Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors, Symposium on VLSI Technology (VLSI), pp.2013226-2013237, 2013.

R. Coquand, S. Barraud, M. Cassé, M. Koyama, V. Maffini-alvaro et al., De Salvo, Low-Temperature Transport Characteristics in SOI and sSOI Nanowires Down to 8nm Width: Evidence of IDS and Mobility Oscillations, Proceedings of the European Solid-State Device Research Conference (ESSDERC), p.2013

R. Coquand, M. Jaud, O. Rozeau, A. Idrissi-eloudrhiri, S. Martinie et al., Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), pp.3-2013
DOI : 10.1109/S3S.2013.6716523

R. Publications-de-journal, M. Coquand, S. Cassé, D. Barraud, V. Cooper et al., Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width, IEEE Transactions on Electron Devices(TED), vol.60, issue.2, p.727732, 2013.

V. Samson, C. Maffini-alvaro, S. Tabone, D. Barnola, G. Munteanu et al., Scaling of high-?/metal-gate TriGate SOI nanowire transistors down to 10nm width, Solid-State Electronics (SSE), vol.88, pp.32-36, 2013.
URL : https://hal.archives-ouvertes.fr/hal-01002171

J. Publications-de-co-auteurs, J. Huguenin, S. Lacord, R. Monfray, T. Coquand et al., Comparative study of circuit perspectives for multi-gate structures at sub-10nm node, Proceedings of the European Solid-State Device Research Conference (ESSDERC), p.107, 2011.

M. Barraud, R. Berthomé, M. Coquand, T. Cassé, M. Ernst et al., Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm, IEEE Electron Device Letters, vol.33, issue.9, p.12251227, 2012.
DOI : 10.1109/LED.2012.2203091

S. Deshpande, X. Barraud, R. Jehl, M. Wacquez, R. Vinet et al., Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp.121-2012
DOI : 10.1109/ESSDERC.2012.6343348

S. Barraud, R. Coquand, M. Casse, M. Koyama, J. Hartmann et al., Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm, IEEE Electron Device Letters, vol.33, issue.11, pp.1526-1528, 2012.
DOI : 10.1109/LED.2012.2212691

M. Koyama, M. Cassé, R. Coquand, S. Barraud, H. Iwai et al., Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs, 2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), pp.73-2012, 2012.
DOI : 10.1109/ESSDERC.2012.6343336

M. Cassé, S. Barraud, C. Leroyer, M. Koyama, R. Coquand et al., Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires, 2012 International Electron Devices Meeting, 2012.
DOI : 10.1109/IEDM.2012.6479119

R. Deshpande, M. Wacquez, X. Vinet, S. Jehl, R. Barraud et al., Faynot, 300 K operating full-CMOS integrated Single Electron Transistor (SET)-FET circuits, IEEE International Electron Devices Meeting (IEDM), 2012.

J. Lacord, J. Huguenin, S. Monfray, R. Coquand, T. Skotnicki et al., Comparative study of circuit perspectives for multi-gate structures at sub-10nm node, Solid-State Electronics, vol.74, pp.25-31, 2012.
DOI : 10.1016/j.sse.2012.04.007

N. Pons, F. Triozon, M. Jaud, R. Coquand, S. Martinie et al., Density Gradient calibration for Tri-Gate SOI transistor, p.2013

S. Deshpande, X. Barraud, R. Jehl, M. Wacquez, R. Vinet et al., Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor, Solid-State Electronics, vol.84, pp.179-184, 2013.
DOI : 10.1016/j.sse.2013.02.015

M. Cassé, S. Barraud, R. Coquand, M. Koyama, D. Cooper et al., (Invited) Strain-Enhanced Performance of Si-Nanowire FETs, ECS Transactions, vol.53, issue.3, pp.125-136, 2013.
DOI : 10.1149/05303.0125ecst

S. Barraud, R. Coquand, J. Hartmann, V. Maffini-alvaro, M. Samson et al., Enhanced Performance of P-FET Omega-Gate SoI Nanowire With Recessed-SiGe Source-Drain Down to 13-nm Gate Length, IEEE Electron Device Letters, vol.34, issue.9, pp.1103-1105, 2013.
DOI : 10.1109/LED.2013.2274172

S. Barraud, R. Coquand, V. Maffini-alvaro, M. Samson, J. Hartmann et al., Scaling of ?-gate SOI nanowire N-and P-FET down to 10nm gate length: Size-and orientation-dependent strain effects, Symposium on VLSI Technology (VLSI), pp.2013230-231, 2013.

M. Koyama, M. Cassé, R. Coquand, S. Barraud, G. Ghibaudo et al., Study of lowfrequency noise in SOI tri-gate silicon nanowire MOSFETs, 22nd International Conference on Noise and Fluctuations (ICNF), 2013.

M. Koyama, M. Cassé, R. Coquand, S. Barraud, C. Vizioz et al., Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs, Solid-State Electronics (SSE), pp.46-52, 2013.
DOI : 10.1016/j.sse.2013.02.024

URL : https://hal.archives-ouvertes.fr/hal-01002176

K. Lepinay, F. Lorut, A. Pofelski, R. Coquand, R. Pantel et al., Defect analysis of a silicon nanowire transistor by STEM XEDS technique: 2D mappings and tomography, p.2013

M. Koyama, M. Cassé, R. Coquand, S. Barraud, G. Ghibaudo et al., Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013.
DOI : 10.1109/ESSDERC.2013.6818878

URL : https://hal.archives-ouvertes.fr/hal-01022530

M. Vinet, V. Deshpande, X. Jehl, R. Wacquez, M. Barraud et al., FDSOI nanowires: An opportunity for hybrid circuit with field effect and single electron transistors, 2013 IEEE International Electron Devices Meeting, 2013.
DOI : 10.1109/IEDM.2013.6724697