Enhancing operating system support for multicore processors by using hardware performance monitoring, ACM SIGOPS Operating Systems Review, vol.43, issue.2, pp.56-65, 2009. ,
DOI : 10.1145/1531793.1531803
Variability in architectural simulations of multi-threaded workloads, Proceedings of the 9th International Symposium on High-Performance Computer Architecture, p.7, 2003. ,
hwloc: A Generic Framework for Managing Hardware Affinities in HPC Applications, 2010 18th Euromicro Conference on Parallel, Distributed and Network-based Processing, pp.180-186, 2010. ,
DOI : 10.1109/PDP.2010.67
URL : https://hal.archives-ouvertes.fr/inria-00429889
Reuse distance as a metric for cache behavior ,
A Scalable Cross-Platform Infrastructure for Application Performance Tuning Using Hardware Counters, ACM/IEEE SC 2000 Conference (SC'00), p.42, 2000. ,
DOI : 10.1109/SC.2000.10029
Follow-on scheduling: Using TLB information to reduce cache misses, Sixteenth Symposium on Operating Systems Principles (SOSP '97 Work in Progress Session, Saint Malo, 1997. ,
StatCache: A probabilistic approach to efficient and accurate data locality analysis, IEEE International Symposium on, ISPASS Performance Analysis of Systems and Software, 2004, pp.20-27, 2004. ,
DOI : 10.1109/ISPASS.2004.1291352
Fast data-locality profiling of native execution, ACM SIGMETRICS Performance Evaluation Review, vol.33, issue.1, pp.169-180, 2005. ,
DOI : 10.1145/1071690.1064232
The PARSEC benchmark suite, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, PACT '08, pp.72-81, 1972. ,
DOI : 10.1145/1454115.1454128
The Performance Implications of Locality Information Usage in Shared-Memory Multiprocessors, Journal of Parallel and Distributed Computing, vol.37, issue.1, pp.113-121, 1996. ,
DOI : 10.1006/jpdc.1996.0112
Parallel Programmability and the Chapel Language, International Journal of High Performance Computing Applications, vol.21, issue.3, pp.291-312, 2007. ,
DOI : 10.1177/1094342007078442
Introduction to UPC and language specification, 1999. ,
Predicting interthread cache contention on a chip multi-processor architecture, Proceedings of the 11th International Symposium on High-Performance Computer ArchitectureHPCA '05), pp.340-351, 2005. ,
DOI : 10.1109/hpca.2005.27
X10: an object-oriented approach to non-uniform cluster computing, Proceedings of the 20th annual ACM SIGPLAN conference on Object-oriented programming, systems, languages, and applications, OOPSLA '05, pp.519-538, 2005. ,
Managing distributed, shared l2 caches through oslevel page allocation, MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp.455-468, 2006. ,
DOI : 10.1109/micro.2006.31
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.137.3652
Estimating cache misses and locality using stack distances, Proceedings of the 17th annual international conference on Supercomputing (CDROM), (ICS '03), pp.150-159, 2003. ,
Exact analysis of the cache behavior of nested loops, Proceedings of the ACM SIGPLAN 2001 conference on Programming language design and implementation, (PLDI '01), pp.286-297, 2001. ,
Parallel Computer Architecture: A Hardware/Software Approach, The Morgan Kaufmann Series in Computer Architecture and Design, 1998. ,
A composable model for analyzing locality of multi-threaded programs, 2009. ,
The Native POSIX Thread Library for Linux, 2003. ,
Reuse distance analysis, 2001. ,
Predicting whole-program locality through reuse distance analysis, Proceedings of the ACM SIGPLAN 2003 conference on Programming language design and implementation, (PLDI '03), pp.245-257, 2003. ,
DOI : 10.1145/781131.781159
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.4.6499
Maximum matching and a polyhedron with 0,1-vertices, Journal of Research of the National Bureau of Standards Section B Mathematics and Mathematical Physics, vol.69, issue.1 and 2, pp.69-70, 1965. ,
DOI : 10.6028/jres.069B.013
The perfmon2 interface specification, 2004. ,
Estimating cache performance for sequential and data parallel programs, Proceedings of the International Conference and Exhibition on High- Performance Computing and NetworkingHPCN Europe '97), pp.840-849, 1997. ,
DOI : 10.1007/BFb0031655
Automatic analytical modeling for the estimation of cache misses, Proceedings of the 1999 International Conference on Parallel Architectures and Compilation TechniquesPACT '99), p.221, 1999. ,
The implementation of the Cilk-5 multithreaded language, Proceedings of the ACM SIGPLAN 1998 conference on Programming language design and implementation, (PLDI '98), pp.212-223, 1998. ,
Some computer organizations and their effectiveness, IEEE Transactions on Computers, vol.21, issue.9, pp.948-960, 1972. ,
Statistically rigorous java performance evaluation, Proceedings of the 22nd annual ACM SIGPLAN conference on Object-oriented programming systems and applications, pp.57-76, 2007. ,
DOI : 10.1145/1297105.1297033
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.103.4204
Cache miss equations: a compiler framework for analyzing and tuning memory behavior, ACM Transactions on Programming Languages and Systems, vol.21, issue.4, pp.703-746, 1999. ,
DOI : 10.1145/325478.325479
The GNU Portable Threads ,
Collective Optimization, the 4th International Conference on High Performance and Embedded Architectures and Compilers (HIPEAC), pp.34-49 ,
DOI : 10.1007/978-3-540-92990-1_5
URL : https://hal.archives-ouvertes.fr/inria-00445326
Variability in the execution of multimedia applications and implications for architecture, Proceedings of the 28th annual international symposium on Computer architectureISCA '01), pp.254-265, 2001. ,
Raced Profiles: Efficient Selection of Competing Compiler Optimizations, Conference on Languages , Compilers, and Tools for Embedded Systems (LCTES '09). ACM SIG- PLAN/SIGBED, 2009. ,
Intel Threading Building Blocks (TBB) for Open Source ,
The OpenMP implementation of NAS parallel benchmarks and its performance, 1999. ,
Near-Optimal Placement of MPI Processes on Hierarchical NUMA Architectures, Proceedings of the 16th international Euro-Par conference on Parallel processing: Part IIEuro-Par'10), pp.199-210, 2010. ,
DOI : 10.1007/978-3-642-15291-7_20
URL : https://hal.archives-ouvertes.fr/inria-00544346
Completing an MIMD multiprocessor taxonomy. SIGARCH Computer Architercture News, pp.44-47, 1988. ,
DOI : 10.1145/48675.48682
Computer Architecture: A Quantitative Approach, pp.978-1558605961, 2002. ,
Is Reuse Distance Applicable to Data Locality Analysis on Chip Multiprocessors?, 19th International Conference on Compiler Construction (CC), pp.264-282, 2010. ,
DOI : 10.1007/978-3-642-11970-5_15
Using OS Observations to Improve Performance in Multicore Systems, IEEE Micro, vol.28, issue.3, pp.54-66, 2008. ,
DOI : 10.1109/MM.2008.48
Performance Implications of Cache Affinity on Multicore Processors, Proceedings of the 14th international Euro-Par conference on Parallel ProcessingEuro-Par '08), pp.151-161, 2008. ,
DOI : 10.1007/978-3-540-85451-7_17
A Fast and High Quality Multilevel Scheme for Partitioning Irregular Graphs, SIAM Journal on Scientific Computing, vol.20, issue.1, pp.359-392, 1998. ,
DOI : 10.1137/S1064827595287997
Multilevel Algorithms for Multi-Constraint Graph Partitioning, Proceedings of the IEEE/ACM SC98 Conference, pp.1-13, 1998. ,
DOI : 10.1109/SC.1998.10018
Parallel multilevel k-way partitioning scheme for irregular graphs, Proceedings of the 1996 ACM/IEEE conference on Supercomputing (CDROM) , Supercomputing '96, pp.96-129, 1998. ,
DOI : 10.1145/369028.369103
Optimizing shared cache behavior of chip multiprocessors, Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, Micro-42, pp.505-516, 2009. ,
DOI : 10.1145/1669112.1669176
autopin ??? Automated Optimization of Thread-to-Core Pinning on Multicore Systems, Transactions on high-performance embedded architectures and compilers III, pp.219-235, 2011. ,
DOI : 10.1007/978-3-540-73940-1_33
Auto-tuning support for manycore applications, ACM SIGOPS Operating Systems Review, vol.43, issue.2, pp.96-97, 2009. ,
DOI : 10.1145/1531793.1531808
The Hungarian Method for the assignment problem, Naval Research Logistics Quarterly, vol.2, pp.83-97, 1955. ,
Cache topology aware computation mapping for multicores, ACM SIGPLAN Notices, vol.45, issue.6, pp.74-85, 2010. ,
DOI : 10.1145/1809028.1806605
Pin: building customized program analysis tools with dynamic instrumentation, Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, (PLDI '05), pp.190-200, 2005. ,
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems, 14th International Symposium on High Performance Computer Architecture, pp.367-378, 2008. ,
Algebraic Riccati equations, 1995. ,
Thread tailor: dynamically weaving threads together for efficient, adaptive parallel applications, Proceedings of the 37th annual international symposium on Computer architectureISCA '10), pp.270-279, 2010. ,
Improving data locality with loop transformations, ACM Transactions on Programming Languages and Systems, vol.18, issue.4, pp.424-453, 1996. ,
DOI : 10.1145/233561.233564
Producing wrong data without doing anything obviously wrong!, Proceedings of the 14th international conference on Architectural support for programming languages and operating systemsASPLOS '09), pp.265-276, 2009. ,
DOI : 10.1145/2528521.1508275
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.163.8395
Evaluation techniques for storage hierarchies, IBM Systems Journal, vol.9, issue.2, pp.78-117, 1970. ,
DOI : 10.1147/sj.92.0078
Design and prototype of a performance tool interface for openmp, The Journal of Supercomputing, vol.23, issue.1, pp.105-128, 2002. ,
DOI : 10.1023/A:1015741304337
Progress in digital integrated electronics, International Electron Devices Meeting, pp.11-13, 1975. ,
A comparison of counting and sampling modes of using performance monitoring hardware, Proceedings of the International Conference on Computational Science-Part II, (ICCS '02), pp.904-912, 2002. ,
The Message Passing Interface Standard ,
Measuring and Analysing the Variations of Program Execution Times on Multicore Platforms: Case Study, 2010. ,
URL : https://hal.archives-ouvertes.fr/inria-00514548
Feedback-directed page placement for ccNUMA via hardware-generated memory traces, Journal of Parallel and Distributed Computing, vol.70, issue.12, pp.1204-1219, 2010. ,
DOI : 10.1016/j.jpdc.2010.08.015
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.217.8586
Dynamic Binary Analysis and Instrumentation, 1994. ,
Co-array Fortran for parallel programming, SIGPLAN Fortran Forum, vol.17, issue.2, pp.1-31, 1998. ,
Valgrind: a framework for heavyweight dynamic binary instrumentation, Proceedings of the 2007 ACM SIGPLAN conference on Programming language design and implementationPLDI '07), pp.89-100, 2007. ,
ForestGOMP: an efficient OpenMP environment for NUMA architectures [Per] Perfctr, International Journal on Parallel Programming, Special Issue on OpenMP, vol.10, issue.385, pp.418-439, 2010. ,
MPC: A Unified Parallel Runtime for Clusters of NUMA Machines, Proceedings of the 14th international Euro-Par conference on Parallel ProcessingEuro-Par '08), pp.78-88, 2008. ,
DOI : 10.1007/978-3-540-85451-7_9
SunOS multi-thread architecture, Proceedings of the Winter 1991 USENIX Conference, pp.65-80, 1991. ,
Utility-based cache partitioning: A low-overhead, high-performance, runtime mechanism to partition shared caches, MICRO 39: Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, pp.423-432, 2006. ,
The Art of Computer Systems Performance Analysis : Techniques for Experimental Design, Measurement, Simulation, and Modelling, 1991. ,
Architectural support for operating system-driven CMP cache management, Proceedings of the 15th international conference on Parallel architectures and compilation techniques , PACT '06, pp.2-12, 2006. ,
DOI : 10.1145/1152154.1152160
A new memory monitoring scheme for memory-aware scheduling and partitioning, Proceedings Eighth International Symposium on High Performance Computer Architecture, p.117, 2002. ,
DOI : 10.1109/HPCA.2002.995703
Thread migration to improve synchronization performance, Workshop on Operating System Interference in High Performance Applications, 2006. ,
Accelerating multicore reuse distance analysis with sampling and parallelization, Proceedings of the 19th international conference on Parallel architectures and compilation techniques, PACT '10, pp.53-64, 2010. ,
DOI : 10.1145/1854273.1854286
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.174.8111
Feedback-directed thread scheduling with memory considerations, Proceedings of the 16th international symposium on High performance distributed computing , HPDC '07, pp.97-106, 2007. ,
DOI : 10.1145/1272366.1272380
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.110.8567
Analytical modeling and optimization for affinity based thread scheduling on multicore systems, 2009 IEEE International Conference on Cluster Computing and Workshops, pp.1-10, 2009. ,
DOI : 10.1109/CLUSTR.2009.5289173
Multicore-aware reuse distance analysis, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), pp.1-8, 2010. ,
DOI : 10.1109/IPDPSW.2010.5470780
Dynamic Partitioning of Shared Cache Memory, The Journal of Supercomputing, vol.28, issue.1, pp.7-26, 2004. ,
DOI : 10.1023/B:SUPE.0000014800.27383.8f
Binding Nested OpenMP Programs on Hierarchical Memory Architectures, International Workshop on OpenMP, pp.29-42, 2010. ,
DOI : 10.1007/978-3-642-13217-9_3
Sur l'equations en matrices px=xq. Comptes Rendus des Séances de l'Académie des Sciences, pp.67-71115, 1884. ,
Data and thread affinity in openmp programs, Proceedings of the 2008 workshop on Memory access on future processors, pp.377-384, 2008. ,
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors, Proceedings of the 2nd ACM SIGOPS/EuroSys European Conference on Computer Systems, pp.47-58, 2007. ,
The TLB slice ? a lowcost high-speed address translation mechanism, Proceedings of the 17th annual international symposium on Computer ArchitectureISCA '90), pp.355-363, 1990. ,
The impact of memory subsystem resource sharing on datacenter applications, Proceeding of the 38th annual international symposium on Computer architectureISCA '11), pp.283-294, 2011. ,
The Speedup-Test, 2010. ,
URL : https://hal.archives-ouvertes.fr/inria-00443839
Julien Worms, and Sébastien Briais. The Speedup-Test: A Statistical Methodology for Program Speedup Analysis and Computation, To appear in the Journal of Concurrency and Computation: Practice and Experience, 2012. ,
Let's study whole-program cache behaviour analytically, Proceedings Eighth International Symposium on High Performance Computer Architecture, p.175, 2002. ,
DOI : 10.1109/HPCA.2002.995708
Performance counters and state sharing annotations: a unified approach to thread locality, Proceedings of the 8th international conference on Architectural support for programming languages and operating systemsASPLOS '98), pp.127-138, 1998. ,
A data locality optimizing algorithm, PLDI '91: Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation, (PLDI '91), pp.30-44, 1991. ,
Can hardware performance counters be trusted?, Proceedings of the 4th International Symposium on Workload Characterization, pp.141-150, 2008. ,
Coherent Profiles: Enabling Efficient Reuse Distance Analysis of Multicore Scaling for Loop-based Parallel Programs, 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011. ,
DOI : 10.1109/PACT.2011.58
Dynamic classification of program memory behaviors in CMPs, Proceedings of CMP-MSI, held in conjunction with ISCA-35, 2008. ,
Titanium: A high-performance java dialect. Concurrency -Practice and Experience, pp.11-13825, 1998. ,
Addressing shared resource contention in multicore processors via scheduling, Proceedings of the 15th edition of ASPLOS on Architectural support for programming languages and operating systemsASPLOS '10), pp.129-142, 2010. ,
Towards practical page coloringbased multicore cache management, Proceedings of the 4th ACM European conference on Computer systems, pp.89-102, 2009. ,
DOI : 10.1145/1519065.1519076
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.156.7988
Accuracy of performance counter measurements, 2009 IEEE International Symposium on Performance Analysis of Systems and Software, pp.23-32, 2009. ,
DOI : 10.1109/ISPASS.2009.4919635
Does cache sharing on modern CMP matter to the performance of contemporary multithreaded programs?, Proceedings of the 15th ACM SIGPLAN symposium on Principles and practice of parallel programmingPPoPP '10), pp.203-212, 2010. ,
Studying inter-core data reuse in multicores, Proceedings of the ACM SIGMETRICS joint international conference on Measurement and modeling of computer systems, SIGMETRICS '11, pp.25-36, 2011. ,
DOI : 10.1145/1993744.1993748
Program locality analysis using reuse distance, ACM Transactions on Programming Languages and Systems, vol.31, issue.6, pp.311-350, 2009. ,
DOI : 10.1145/1552309.1552310