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Theses Year : 2012

Bipartite edge coloring approach for designing parallel hardware interleaver architecture

Une approche de coloriage d’arrêtes pour la conception d’architectures parallèles d’entrelaceurs matériels


Nowadays, Turbo and LDPC codes are two families of codes that are extensively used in current communication standards due to their excellent error correction capabilities. However, hardware design of coders and decoders for high data rate applications is not a straightforward process. For high data rates, decoders are implemented on parallel architectures in which more than one processing elements decode the received data. To achieve high memory bandwidth, the main memory is divided into smaller memory banks so that multiple data values can be fetched from or stored to memory concurrently. However, due to scrambling caused by interleaving law, this parallelization results in communication or memory access conflicts which occur when multiple data values are fetched from or stored in the same memory bank at the same time. This problem is called Memory conflict Problem. It increases latency of memory accesses due to the presence of conflict management mechanisms in communication network and unfortunately decreases system throughput while augmenting system cost. To tackle the memory conflict problems, three different types of approaches are used in literature. In first type of approaches, different algorithms to construct conflict free interleaving law are proposed. The main reason to develop these techniques is to construct "architecture friendly" codes with good error correction capabilities in order to reduce hardware cost. However, architectural constraints applied during code design may impede error correction performance of the codes. In a second type of approaches, different design innovations are introduced to tackle memory conflict problem. Flexible and scalable interconnection network with sufficient path diversity and additional storing elements are introduced to handle memory conflicts. However, flexible networks require large silicon area and cost. In addition, delay introduced due to conflict management mechanisms degrades the maximum throughput and makes these approaches inefficient for high data rate and low power applications. In third type of approaches deals with algorithms that assign data in memory in such a manner that all the processing elements can access memory banks concurrently without any conflict. The benefit of this technique is that decoder implementation does not need any specific network and extra storage elements to support particular interleaving law. However, till now no algorithm exists that can solve memory mapping problem for both turbo and LDPC codes in polynomial time. The work presented in this thesis belongs to the last type of approaches. We propose several methods based on graph theory to solve memory mapping problem for both turbo and LDPC codes. Different formal models based on bipartite and tripartite graphs along with different algorithms to color the edges of these graphs are detailed. The complete path we followed before it is possible to solve mapping problem in polynomial time is hence presented. For the first two approaches, mapping problem is modeled as bipartite graph and then each graph is divided into different sub-graphs in order to facilitate the coloring of the edges. First approach deals with Turbo codes and uses transportation problem algorithms to divide and color the bipartite graph. It can find memory mapping that supports particular interconnection network if the interleaving rule of the application allows it. Second approach solves memory mapping problem for LDPC codes using two different complex algorithms to partition and color each partition. In the third algorithm, each time instance and edge is divided into two parts to model our problem as tripartite graph. Tripartite graph is partitioned into different sub-graphs by using an algorithm based on divide and conquer strategy. Then each subgraph is colored individually by using a simple algorithm to find a conflict free memory mapping for both Turbo and LDPC codes. Finally, in the last approach tripartite graph is transformed into bipartite graph on which coloring algorithm based on Euler partitioning principle is applied to find memory mapping in polynomial time. Several experiments have been performed using interleaving laws coming from different communication standards to show the interest of the proposed mapping methods. All the experiments have been done by using a software tool we developed. This tool first finds conflict free memory mapping and then generates VHDL files that can be synthesized to design complete architecture i.e. network, memory banks and associated controllers. In first experiment, bit interleaver used in Ultra Wide Band (UWB) interleaver is considered and a barrel shifter is used as constraint to design the interconnection network. Results are compared regarding area and runtime with state of the art solutions. In second experiments, a turbo interleaving law defined in High Speed Packet Access (HSPA) standard is used as test case. Memory mapping problems have been solved and associated architectures have been generated for this interleaving law which is not conflict free for any type of parallelism used in turbo decoding. Results are compared with techniques used in state of the art in terms of runtime and area. Third experiment focuses on LDPC. First, last algorithm we proposed is used to find conflict free memory mapping for non-binary LDPC codes defined in the DaVinci Codes FP7 ICT European project. Then, conflict free memory mapping have also been found for partially parallel architecture of LDPC codes used in WiMAX and WiFi for different level of parallelism. It is shown that the proposed algorithm can be used to map data in memory banks for any structured codes used in current and future standards for partially parallel architecture. In last experiment, thanks to the proposed approach we explored the design space of Quadratic Permutation Polynomial (QPP) interleaver that is used in 3GPP-LTE standard. The QPP interleaver is maximum contention-free i.e., for every window size W which is a factor of the interleaver length N, the interleaver is contention free. However, when trellis and recursive units parallelism are also included in each SISO, QPP interleaver is no more contention-free. Results highlight tradeoffs between area and performances based on for different radixes, parallelisms, scheduling (replica versus butterfly)...
Pour tirer partie leurs excellentes performances, les standards de communications actuels intègrent des algorithmes de correction d’erreurs de type Turbo-Code ou LDPC. Toutefois, leur réalisation matérielle implique de nouveaux défis à relever pour supporter les applications très hauts débit. En effet, pour ces applications la mémoire principale est partitionnée en bancs mémoires plus petits et les données sont accédées en parallèle pour atteindre les débits applicatifs requis. Ce type d’architecture entraine toutefois des conflits d’accès mémoire, du fait des accès aux données définis dans les standards (Turbo-Code ou LDPC). Ceci peut générer un surcoût en termes de surface et de latence dans l’architecture. Au cours de cette thèse, différentes approches ont étés explorées pour déterminer un placement des données dans les bancs mémoires garantissant des accès sans conflits. Toutes ces approches se basent sur des approches de théorie des graphes et fonctionnent en deux étapes : dans un premier temps les accès mémoires sont modélisés avec un graphe (bipartite ou tripartite). Ensuite, différents algorithmes sont proposés pour placer les données dans les bancs mémoires. Plusieurs expériences ont étés réalisées, grâce à des logiciels réalisés au cours de cette thèse. Ces logiciels déterminent un placement mémoire sans conflits puis génèrent les descriptions VHDL de l’architecture, i.e. réseau, bancs mémoires et contrôleurs associés. Ces expériences ont portées sur différents standards de communication tels que UWB, HSPA, LDPC non binaires et système 4G. Elles ont démontrées la pertinence des solutions retenues et leur efficacité par rapport aux approches de l’état de l’art.
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tel-00790045 , version 1 (19-02-2013)


  • HAL Id : tel-00790045 , version 1


Sani Awais Hussein. Bipartite edge coloring approach for designing parallel hardware interleaver architecture. Hardware Architecture [cs.AR]. Université de Bretagne Sud, 2012. English. ⟨NNT : ⟩. ⟨tel-00790045⟩
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