Skip to Main content Skip to Navigation
New interface
Theses

High Level Hardware Synthesis of RVC Dataflow Programs

Abstract : The evolution of video processing algorithms involved the advent of several standards. These standards present many common algorithms but designers are not able to reuse them because of their monolithic description. To solve this problem, ISO/IEC MPEG committee created the Reconfigurable Video Coding (RVC) standard based on the idea that processing algorithms can be defined as a library of components defined following the Dataflow Model of Computation and that can be updated separately. Thus, these components of the modular library are standardized instead of the whole decoder. A Dataflow program can be defined as a directed graph where the vertices represent the processes (actors) to be executed and the edges represent the FIFOs used for the communication. The exchanged data is called tokens. This concept insured that the processes are completely independent and only the presence of tokens which allows the firing of a process. To translate this Model of Computation into a functional description, the Cal actor Language (CAL) is considered in this thesis work. This language is standardized by the MPEG-RVC standard. This standard is supported with a complete infrastructure to design and compile the RVC-CAL into hardware and software implementations. The drawback is that the existing hardware compilers present several limitations especially for the validation and the compilation of high level features of the language. For the validation, we propose a functional methodology that allows the validation of the algorithms in all the conception steps. We show in this thesis the important impact of this methodology to reduce the conception time. Concerning the hardware compilation limitations, we introduce an automatic transformation integrated in the code of an RVC-CAL compiler called Orcc (Open RVC-CAL Compiler). This transformation detects the non compliant features and applies the required transformations in the intermediates representation of Orcc to obtain a synthesizable code while keeping the same global behavior of the actor. This transformation solved the main issue of the hardware generation from Dataflow programs. To validate and assess these methodologies, we applied them on the MPEG-4 Part 2 Simple Profile decoder and the LAR still image codec. We present comparison studies for these application contexts.
Complete list of metadata

Cited literature [82 references]  Display  Hide  Download

https://theses.hal.science/tel-00827163
Contributor : Khaled Jerbi Connect in order to contact the contributor
Submitted on : Tuesday, May 28, 2013 - 10:32:14 PM
Last modification on : Wednesday, April 27, 2022 - 4:05:45 AM
Long-term archiving on: : Thursday, August 29, 2013 - 9:50:15 AM

Identifiers

  • HAL Id : tel-00827163, version 1

Citation

Khaled Jerbi. High Level Hardware Synthesis of RVC Dataflow Programs. Signal and Image Processing. INSA de Rennes, 2012. English. ⟨NNT : ⟩. ⟨tel-00827163⟩

Share

Metrics

Record views

397

Files downloads

479