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Stratégie de réduction des cycles thermiques pour systèmes temps-réel multiprocesseurs sur puce

Abstract : Increasing the density of transistors in electronic circuits leads to an increase in energy consumption resulting in more complex thermal phenomena to master. For systems embedded in environments where the ambient temperature can vary in large range (e.g. automotive), these thermal effects can induce reliability problems. Among classical failure mechanisms thermal cycles (CTs) produce deformations in materials and play a major role in the cracking of the metal layers in the chip. The aim of the thesis is to propose a reduction technique of CTs suffered by the processor cores in a multiprocessor on chip architecture such that real-time application constraints are met. The example of the Freescale MPC5517 circuit has been considered. In a first step a thermal model of this circuit was developed. This was achieved from measurements taken by a thermal camera on a decapsulated circuit. Next, a simulation environment has been implemented allowing both the analysis of thermal behavior and the scheduling of tasks so as to highlight the influence of temperature on the dissipated power. A global heuristic to reduce both the CTs and the maximum temperature of processors has been studied. It takes into account variations in the ambient temperature and is based on DVFS and DPM techniques. Simulation results with global scheduling algorithms RM, EDF and EDZL and different processor loads (for a MPC5517 type circuit and a T1 UltraSparc from Sun Microsystems) illustrate the effectiveness of the proposed technique.
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Submitted on : Sunday, March 2, 2014 - 1:18:02 AM
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  • HAL Id : tel-00947611, version 2



Khaled Baati. Stratégie de réduction des cycles thermiques pour systèmes temps-réel multiprocesseurs sur puce. Autre [cs.OH]. Université Nice Sophia Antipolis, 2013. Français. ⟨NNT : 2013NICE4141⟩. ⟨tel-00947611v2⟩



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