In the automotive industry, the trend being to develop smartsensors and actuators, the on-board electronic has been ever more an artful workto combine analog electronics and the digital one. While many monitoring andcontrol systems play a crucial role as well for the safety as for the comfort of passengers,small components, like ADCs, are mandatory as a building block or as anessential functionality integrated into smart actuators. To that extent, a low-cost,fast and accurate analog to digital converter operating in those harsh conditionsis a good ally for equipment manufacturers. To decrease the cost, the area is ofprimary concern. Considering re-use of the ADC as an IP-bloc, the area has beenlimited to less than half a square millimeter for an low-oversampling ratio of 5 tooutput a 12-bit code at a sample rate of 20 MSamples/s, over a wide temperaturerange from-40°C to 175°C.This work focuses on the design of high-precision, high-speed and energyefficient ADC under the harsh environment the automotive one represents. Ourmain contribution relies on the development of an new hybrid topology proposalusing 3 stages to cope with such constraints based on a top-down approach: A firstcounting stage inherently linear, an algorithmic stage allowing to increase rapidlythe precision, and a SAR stage, ideal in terms of area and consumption, for a lownumber of bits.Based on a 40 years literature review, a new topology proposal has been validatedby checking its static metric of non-linearity (DNL, INL) at different level ofmodelisation. Starting by a MATLAB implementation without analog limitations,we refined step by step the model tillwe reach a transistor level of the ADC. Thence,Verilog-A model allows us to fix the minimum requirements of the key analog buildingblocks, to wit comparators and OTA. The latter has been analysed in order tolimit the settling error sensitivity to the temperature. Laid-out, parasitic extractedsimulation results of these considering PVT variations, they replace then previoushigh-level model to give final performances. Meanwhile, two well-known comparatorarchitectures have been assessed as IP blocs inside a first test chip. To performthe offset extraction, both a conventional and a feedback loop have been inspected.To assess, the delay a new asynchronous circuit has been proposed. A secondchip tests the sensitivity of the SAR to validate both the pseudo-asynchronousdigital scheme, and a Double-Tail comparator in real operating conditions.For comparators, the new differential measurement circuit of the delaydemonstrate an accuracy of 60 ps in the worst case, over a large temperature rangefor the smallest chip area known with respect to the technology node size. Thetemperature variation of the delay being temperature dependent, the choice of aStrong-ARM or a Double-Tail hinge on the noise, power, supply voltage, and kickbackspecification. For standard power supply voltage, the Strong-ARM latch targetslow-power systems application with a high tolerance for differential kickback.To the contrary, a Double-Tail latch allows lower power supply voltage range, withlow-differential kickback. Otherwise, the Double-Tail exhibit a higher noise due tothe integration in its first stage. Tested from -40°C to 200°C, the last stage of theproposed ADC topology does not need calibration up to 180°C. The encouragingresults on this stage allows the re-use of the SAR to calibrate the previous stages.And considering the ADC, we estimate a possible resolution of 11.2-bits in 5 clockcycles per sample with an extension to 13.3-bits in 6 clock cycles with an estimatedarea of 0.12 mm2.The ADC test chip not being fabricated yet, a first step is the characterizationof the ADC. From the results of the planned measurement session, the maingoal is to push the architecture at higher sampling rates to then leverage the digitalprocessing to enhance the sampling rate without changing the analog.